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1. 发明授权

US5557580A Word line driving circuit 失效
标题翻译：字线驱动电路
公开(公告)号：US5557580A
公开(公告)日：1996-09-17
申请号：US292452
申请日：1994-08-18
申请人： Shigeki Numaga , Shunichi Sukegawa , Takashi Inui , Yukihide Suzuki , Kiyoshi Nakai
发明人： Shigeki Numaga , Shunichi Sukegawa , Takashi Inui , Yukihide Suzuki , Kiyoshi Nakai
IPC分类号： G11C11/407 , G11C8/08 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C8/00 , G11C7/00
CPC分类号： G11C8/08
摘要： A word line driving circuit which effectively prevents ground noise during word line discharge along with accommodating the narrowing of pitch in the word lines by making the layout area of the word line driver small. The word line driving circuit includes n-type MOS transistor 14 and p-type MOS transistor 12. The drain terminal of n-type MOS transistor 14 and drain terminal of p-type MOS transistor 12 in word line driver 10 are connected to the base terminal of word line WLi. The output terminal of an output transistor driving circuit 16 is connected to the source terminal of p-type MOS transistor 12, and the output terminal of a first output transistor controlling circuit 18 is connected to the gate terminal. The output terminal of a second output transistor controlling circuit 20 is connected to the gate terminal of n-type MOS transistor 14, and a ground terminal 22 as a reference potential terminal for leading in the electric current is connected to the source terminal.
摘要翻译：一种字线驱动电路，通过使字线驱动器的布局面积小，能够有效地防止字线放电期间的接地噪声，同时容纳字线中的音调变窄。字线驱动电路包括n型MOS晶体管14和p型MOS晶体管12. n型MOS晶体管14的漏极端子和字线驱动器10中的p型MOS晶体管12的漏极端子连接到基极字线WLi的终端。输出晶体管驱动电路16的输出端子与p型MOS晶体管12的源极端子连接，第一输出晶体管控制电路18的输出端子与栅极端子连接。第二输出晶体管控制电路20的输出端子与n型MOS晶体管14的栅极端子连接，作为引导电流的基准电位端子的接地端子22与源极端子连接。

2. 发明授权

US06249472B1 Semiconductor memory device with antifuse 有权
标题翻译：具有反熔丝的半导体存储器件
公开(公告)号：US06249472B1
公开(公告)日：2001-06-19
申请号：US09215109
申请日：1998-12-18
申请人： Yoshimitsu Tamura , Takumi Nasu , Hideyuki Fukuhara , Shigeki Numaga
发明人： Yoshimitsu Tamura , Takumi Nasu , Hideyuki Fukuhara , Shigeki Numaga
IPC分类号： G11C700
CPC分类号： H01L27/10882 , G11C17/18 , H01L23/5252 , H01L27/10852 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： The objective of the invention is to provide a type of semiconductor memory device whose antifuse can be formed without any additional film manufacturing process. A first electrode is formed by a first polysilicon film 37 formed on semiconductor substrate 30 and a second polysilicon film 39 deposited on the surface of the first polysilicon film. The first electrode, a dielectric film formed on the surface of the first electrode, and a second electrode form capacitor 11 in the memory cell. An antifuse 12 with the same configuration as capacitor 11 is formed in the semiconductor memory device. Because there is no need to use an additional film, the manufacturing cost is low, and antifuse 12 can be easily arranged. It is also possible to form antifuse 13 by forming instead of depositing the second polysilicon film 39 on the surface of the first polysilicon film 39.
摘要翻译：本发明的目的是提供一种半导体存储器件，其反熔丝可以在没有任何附加的膜制造工艺的情况下形成。第一电极由形成在半导体衬底30上的第一多晶硅膜37和沉积在第一多晶硅膜的表面上的第二多晶硅膜39形成。第一电极，形成在第一电极的表面上的电介质膜和存储单元中的第二电极形成电容器11。在半导体存储器件中形成具有与电容器11相同结构的反熔丝12。因为不需要使用额外的薄膜，所以制造成本低，并且可以容易地布置反熔丝12。还可以通过形成反熔丝13而不是在第一多晶硅膜39的表面上沉积第二多晶硅膜39。

3. 发明授权

US5670976A Spatial light modulator having redundant memory cells 失效
标题翻译：具有冗余存储单元的空间光调制器
公开(公告)号：US5670976A
公开(公告)日：1997-09-23
申请号：US395545
申请日：1995-02-28
申请人： Edison H. Chiu , Shigeki Numaga , Takeshi Honzawa
发明人： Edison H. Chiu , Shigeki Numaga , Takeshi Honzawa
IPC分类号： G09G3/34 , H04N9/30
CPC分类号： H04N9/30 , G09G3/34 , G09G2300/0842 , G09G2310/0267 , G09G2330/08
摘要： A spatial light modulator (10) of the DMD type having an array of memory cells (16) controlling an array of pixels (12). The memory cell array (16) has several integral, interleaved spare rows of memory cells MR (R1), MR (R2), and MR (R3), which can be selectively utilized to replace a defective row of primary memory cells. A fused row address mapping logic circuit (40) includes a network of fuses (F0-F12) and controls the implementation of memory cells, as well as the mapping of address signals to the memory cells as a function of inputs (R0-R11) received from a row decoder circuit (20). This circuit (40) is transparent to the row address decoder circuit (20). The present invention is suitable for large spatial light modulators compatible with high definition television (HDTV). High yield devices can be obtained with the present invention.
摘要翻译： DMD类型的空间光调制器（10）具有控制像素阵列（12）的存储单元阵列（16）。存储单元阵列（16）具有存储单元MR（R1），MR（R2）和MR（R3）的几个整数交错的备用行，其可以有选择地用于替换主存储单元的有缺陷的行。融合行地址映射逻辑电路（40）包括熔丝网（F0-F12），并控制存储器单元的实现，以及作为输入（R0-R11）的函数将地址信号映射到存储器单元，从行解码器电路（20）接收。该电路（40）对行地址解码电路（20）是透明的。本发明适用于与高分辨率电视（HDTV）兼容的大型空间光调制器。本发明可以获得高产量的装置。

4. 发明授权

US5615156A Semiconductor memory device having plural memory mats with centrally located reserve bit or word lines 失效
标题翻译：半导体存储器件具有多个具有中心位置的保留位或字线的存储垫
公开(公告)号：US5615156A
公开(公告)日：1997-03-25
申请号：US250130
申请日：1994-05-27
申请人： Hiroyuki Yoshida , Takashi Inui , Shigeki Numaga , Kiyoshi Nakai , Yukihide Suzuki
发明人： Hiroyuki Yoshida , Takashi Inui , Shigeki Numaga , Kiyoshi Nakai , Yukihide Suzuki
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C29/80
摘要： A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approximately in a central portion of a memory mat. Because of a low probability of defect occurrence in the reserve word lines or bit lines, the probability of defect occurrence can be made low when a defective word line or bit line is replaced with a reserve word line or bit line.
摘要翻译：具有备用位线或字线的半导体存储器件，用于替换有缺陷的位线或字线，这些位线或字线可以增加缺陷消除概率并提高操作余量。保留位线或字线大致设置在存储垫的中央部分。由于在备用字线或位线中存在缺陷发生的可能性低的情况，当用保留字线或位线替换缺陷字线或位线时，可能会使缺陷发生的概率变低。

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