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1. 发明授权

US5768214A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5768214A
公开(公告)日：1998-06-16
申请号：US689548
申请日：1996-08-09
申请人： Ken Saitoh , Shunichi Sukegawa , Tadashi Tachibana , Makoto Saeki , Yukihide Suzuki
发明人： Ken Saitoh , Shunichi Sukegawa , Tadashi Tachibana , Makoto Saeki , Yukihide Suzuki
IPC分类号： G11C11/41 , G11C7/06 , G11C8/18 , G11C11/409 , G11C8/00
CPC分类号： G11C8/18 , G11C7/06
摘要： A semiconductor memory device in which erroneous operation with respect to undesired level changes of the input address signal is prevented, and appropriate operation of the main amplifier is ensured. The semiconductor memory device has a main amplifier activating pulse generator 112' which includes response sensitivity reduction circuit 10, response sensitivity selector 12, and main amplifier activating pulse generator 14. The response sensitivity reduction circuit 10 can reduce the response sensitivity or input sensitivity of the circuit 112' with respect to an input address transition detection pulse ATD. The response sensitivity selector 12 selects either a first input terminal A1 or a second input terminal A2, depending on the output state of the main amplifier activating pulse generator 14. Consequently, when there is no output of a main amplifier activating pulse MA from the main amplifier activating pulse generator 14, the response sensitivity selector 12 switches to first input terminal A1 to select response sensitivity reduction circuit 10; when a main amplifier activating pulse MA is output, the selector 12 switches to second input terminal A2 to select bypass circuit 11.
摘要翻译：一种半导体存储器件，其中防止了与输入地址信号的不期望的电平变化有关的错误操作，并且确保了主放大器的适当的操作。半导体存储器件具有主放大器激活脉冲发生器112'，其包括响应灵敏度降低电路10，响应灵敏度选择器12和主放大器激活脉冲发生器14.响应灵敏度降低电路10可以降低响应灵敏度降低电路10的响应灵敏度或输入灵敏度电路112'相对于输入地址转换检测脉冲ATD。响应灵敏度选择器12根据主放大器激活脉冲发生器14的输出状态选择第一输入端子A1或第二输入端子A2。因此，当没有主放大器从主振荡器激活脉冲MA的输出放大器激活脉冲发生器14，响应灵敏度选择器12切换到第一输入端子A1以选择响应灵敏度降低电路10; 当输出主放大器激活脉冲MA时，选择器12切换到第二输入端A2以选择旁路电路11。

2. 发明授权

US6166977A Address controlled sense amplifier overdrive timing for semiconductor memory device 有权
标题翻译：半导体存储器件的地址控制读出放大器过驱动定时
公开(公告)号：US6166977A
公开(公告)日：2000-12-26
申请号：US272872
申请日：1999-03-19
申请人： Ken Saitoh , Shoji Wada
发明人： Ken Saitoh , Shoji Wada
IPC分类号： G11C7/06 , G11C7/22 , G11C11/4091 , G11C7/00
CPC分类号： G11C11/4091 , G11C7/06 , G11C7/22
摘要： A dynamic random access memory device having a number of sense amplifier banks (404a-404h) is disclosed. Each sense amplifier bank (404a-404h) has an associated memory array (402a-402h) and supply switch (406a-406h). In a given sense operation, data signals are coupled from a memory array (402a-402h) to its associated sense amplifier bank (404a-404h). Selection of the memory array (402a-402h) is determined by address signals (MS0-MS7). The supply switches (406a-406h) provide a sense amplifier supply voltage at a supply node (708) of its associated sense amplifier bank (404a-404h). At the initial portion of a sense operation, the supply switch (406a-406h) couples the high power supply voltage (VDD) to its associated supply node (708). After a predetermined time period, the supply switch couples a reduced array voltage (VDL) to its associated supply node (708). The switching operation is determined by an overdrive signal (SAOV). The timing of the SAOV signal is based upon the location of the memory array (402a-402h) which is being accessed in the sense operation.
摘要翻译：公开了一种具有多个读出放大器组（404a-404h）的动态随机存取存储器件。每个读出放大器组（404a-404h）具有相关联的存储器阵列（402a-402h）和电源开关（406a-406h）。在给定的感测操作中，数据信号从存储器阵列（402a-402h）耦合到其相关联的读出放大器组（404a-404h）。存储器阵列（402a-402h）的选择由地址信号（MS0-MS7）确定。电源开关（406a-406h）在其相关读出放大器组（404a-404h）的电源节点（708）处提供感测放大器电源电压。在感测操作的初始部分，电源开关（406a-406h）将高电源电压（VDD）耦合到其相关联的电源节点（708）。在预定时间段之后，电源开关将降低的阵列电压（VDL）耦合到其相关联的电源节点（708）。切换操作由过驱动信号（SAOV）决定。 SAOV信号的定时基于在感测操作中被访问的存储器阵列（402a-402h）的位置。

3. 发明授权

US5831925A Memory configuration circuit and method 失效
标题翻译：内存配置电路和方法
公开(公告)号：US5831925A
公开(公告)日：1998-11-03
申请号：US982672
申请日：1997-12-02
申请人： David R. Brown , Shoji Wada , Kazuya Ito , Yasuhito Ichimura , Ken Saitoh
发明人： David R. Brown , Shoji Wada , Kazuya Ito , Yasuhito Ichimura , Ken Saitoh
IPC分类号： G11C11/41 , G06F12/06 , G11C7/10 , G11C8/12 , G11C11/401 , G11C8/00 , G11C7/00
CPC分类号： G11C8/12 , G11C7/1045
摘要： A memory circuit includes a bond option circuit 106 having an input and an output, and row control circuitry 100 coupled to the output of the bond option circuit, the row control circuitry including address terminals, A12 and A13. The memory circuit also includes column control circuitry 102 coupled to the output of the bond option circuit, the column control circuitry 102 also including address terminals, A12 and A13. A memory cell array is coupled to the row control and column control circuitry and is arranged in a first plurality of banks of memory cells, the banks being selectable by a combination of address signals on the address terminals of the row control and column control circuitry. In response to a first signal at the input of the bond option circuit 106, the bond option circuit produces a second signal at the output of the bond option circuit that is coupled to the row control 100 and column control 102 circuitry. In response to the second signal, the row control and column control circuitry makes the banks of the array selectable in a second plurality. For example, the array may originally be arranged in four banks, but by the placing the proper signal at the input of the bond option circuit, the array is selectable as a two-bank array.
摘要翻译：存储器电路包括具有输入和输出的接合选择电路106，以及耦合到接合选择电路的输出的行控制电路100，行控制电路包括地址端子A12和A13。存储器电路还包括耦合到键选择电路的输出的列控制电路102，列控制电路102还包括地址端子A12和A13。存储单元阵列耦合到行控制和列控制电路，并且被布置在第一多个存储单元组中，这些存储体可以由行控制和列控制电路的地址端上的地址信号的组合来选择。响应于接合选择电路106的输入处的第一信号，接合选择电路在耦合到行控制器100和列控制器102电路的接合选择电路的输出处产生第二信号。响应于第二信号，行控制和列控制电路使得阵列的组可选择在第二组中。例如，阵列最初可以排列成四个组，但是通过将适当的信号放置在键合选项电路的输入处，阵列可以选择为双组阵列。

4. 发明授权

US06616462B2 Convertible multi-diameter sleeve for optical fiber connectors 失效
标题翻译：用于光纤连接器的可转换多直径套管
公开(公告)号：US06616462B2
公开(公告)日：2003-09-09
申请号：US09944088
申请日：2001-09-04
申请人： Ken Saitoh
发明人： Ken Saitoh
IPC分类号： G02B638
CPC分类号： G02B6/3877
摘要： This invention is a convertible multi-diameter sleeve for optical fiber connectors to allow optical fiber cables with plug ferrules of different internal and external diameters to be pushed into the sleeve and connected with precise core alignment keeping stable conditions. The sleeve has at least one slot extending part way along the length of the sleeve.
摘要翻译：本发明是用于光纤连接器的可转换多直径套管，其允许具有不同内部和外部直径的插头套管的光纤电缆被推入套筒中，并与精确的芯线对准保持稳定状态。套筒具有至少一个沿套筒的长度部分延伸的槽。

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