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1. 发明授权

US07504337B2 IC chip uniform delayering methods 失效
标题翻译： IC芯片均匀推迟方法
公开(公告)号：US07504337B2
公开(公告)日：2009-03-17
申请号：US11690432
申请日：2007-03-23
申请人： Keith E. Barton , Thomas A. Bauer , Stanley J. Klepeis , John A. Miller , Yun-Yu Wang
发明人： Keith E. Barton , Thomas A. Bauer , Stanley J. Klepeis , John A. Miller , Yun-Yu Wang
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： G01N1/32 , H01L22/24
摘要： Methods of uniformly delayering an IC chip are disclosed. One embodiment includes: performing an ash on the wafer including an Al layer thereof and etching the Al layer; polishing an edge of the wafer using a slurry including an approximately 30 μm polishing particles; removing the aluminum layer and at least one metal layer by polishing using a slurry including approximately 9 μm diamond polishing particles and a non-abrasive backside of a polishing sheet; removing any remaining metal layers to a first metal layer by polishing using a slurry including approximately 3 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; removing any scratches by polishing using a slurry including approximately 1 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; and removing the first metal layer to a polyconductor layer by polishing using a colloidal slurry including approximately 0.25 μm diamond polishing particles.
摘要翻译：公开了均匀地延迟IC芯片的方法。一个实施例包括：在包括其Al层的晶片上执行灰分并蚀刻Al层; 使用包含约30μm的抛光颗粒的浆料抛光晶片的边缘; 通过使用包含大约9μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来去除铝层和至少一个金属层; 通过使用包含大约3μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光，将任何剩余的金属层除去到第一金属层; 通过使用包括大约1毫米金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来除去任何划痕; 并且通过使用包含大约0.25μm金刚石抛光颗粒的胶体浆料进行抛光将第一金属层去除到多导体层。

2. 发明申请

US20080233751A1 IC CHIP UNIFORM DELAYERING METHODS 失效
标题翻译： IC芯片均匀延迟方法
公开(公告)号：US20080233751A1
公开(公告)日：2008-09-25
申请号：US11690432
申请日：2007-03-23
申请人： Keith E. Barton , Thomas A. Bauer , Stanley J. Klepeis , John A. Miller , Yun-Yu Wang
发明人： Keith E. Barton , Thomas A. Bauer , Stanley J. Klepeis , John A. Miller , Yun-Yu Wang
IPC分类号： H01L21/461
CPC分类号： G01N1/32 , H01L22/24
摘要： Methods of uniformly delayering an IC chip are disclosed. One embodiment includes: performing an ash on the wafer including an Al layer thereof and etching the Al layer; polishing an edge of the wafer using a slurry including an approximately 30 μm polishing particles; removing the aluminum layer and at least one metal layer by polishing using a slurry including approximately 9 μm diamond polishing particles and a non-abrasive backside of a polishing sheet; removing any remaining metal layers to a first metal layer by polishing using a slurry including approximately 3 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; removing any scratches by polishing using a slurry including approximately 1 μm diamond polishing particles and the non-abrasive backside of a polishing sheet; and removing the first metal layer to a polyconductor layer by polishing using a colloidal slurry including approximately 0.25 μm diamond polishing particles.
摘要翻译：公开了均匀地延迟IC芯片的方法。一个实施例包括：在包括其Al层的晶片上执行灰分并蚀刻Al层; 使用包含约30μm的抛光颗粒的浆料抛光晶片的边缘; 通过使用包含大约9μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来去除铝层和至少一个金属层; 通过使用包含大约3μm的金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光，将任何剩余的金属层除去到第一金属层; 通过使用包括大约1毫米金刚石抛光颗粒和抛光片的非研磨背面的浆料进行抛光来除去任何划痕; 并且通过使用包含大约0.25μm金刚石抛光颗粒的胶体浆料进行抛光将第一金属层去除到多导体层。

3. 发明授权

US06661097B1 Ti liner for copper interconnect with low-k dielectric 失效
标题翻译：用于低k电介质的铜互连的Ti衬垫
公开(公告)号：US06661097B1
公开(公告)日：2003-12-09
申请号：US10287155
申请日：2002-11-01
申请人： Larry Clevenger , Stanley J. Klepeis , Hsiao-Ling Lu , Jeffrey R. Marino , Andrew Herbert Simon , Yun-Yu Wang , Kwong Hon Wong , Chih-Chao Yang
发明人： Larry Clevenger , Stanley J. Klepeis , Hsiao-Ling Lu , Jeffrey R. Marino , Andrew Herbert Simon , Yun-Yu Wang , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In copper backend integrated circuit technology, advanced technology using low-k organic-based interlayer dielectrics have a problem of carbon contamination that dos not occur in circuits using oxide as dielectric. A composite liner layer for the copper lines uses Ti as the bottom layer, which has the property of gettering carbon and other contaminants. The known problem with Ti of reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper.
摘要翻译：在铜后端集成电路技术中，使用低k有机基层间电介质的先进技术具有碳污染的问题，在使用氧化物作为电介质的电路中不会发生这种问题。用于铜线的复合衬里层使用Ti作为底层，其具有吸除碳和其它污染物的性质。通过添加一层分离Ti和铜的TiN层，避免了与铜反应形成高电阻率化合物的Ti的已知问题。

4. 发明授权

US07560692B2 Method of TEM sample preparation for electron holography for semiconductor devices 失效
标题翻译：半导体器件电子全息术的TEM样品制备方法
公开(公告)号：US07560692B2
公开(公告)日：2009-07-14
申请号：US11617386
申请日：2006-12-28
申请人： Keith E. Barton , Steven H. Boettcher , John G. Gaudiello , Leon J. Kimball , Yun-Yu Wang
发明人： Keith E. Barton , Steven H. Boettcher , John G. Gaudiello , Leon J. Kimball , Yun-Yu Wang
IPC分类号： G01N1/32 , G01N23/04
CPC分类号： G01N1/2806
摘要： A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. The TEOS oxide marker is readily visible during the polish, has a similar polish rate as a semiconductor material, and reduces contamination during sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.
摘要翻译：适用于电子全息术的高品质电子显微镜样品通过形成填充有TEOS氧化物的标记物，并通过反复施加多层粘合剂，然后在每次涂布之后进行相对低温固化来制备。 TEOS氧化物标记在抛光期间容易看到，具有与半导体材料相似的抛光速率，并减少样品制备过程中的污染。通过相对低温固化分离的粘合剂的重复施加增加了粘合剂材料对半导体材料的粘合强度，而不会使其变得太脆。这导致样品制备过程的改进的控制和产率。

5. 发明授权

US07214935B2 Transmission electron microscopy sample preparation method for electron holography 失效
标题翻译：透射电子显微镜用于电子全息术的样品制备方法
公开(公告)号：US07214935B2
公开(公告)日：2007-05-08
申请号：US10711690
申请日：2004-09-30
申请人： Thomas A. Bauer , Steven H. Boettcher , Anthony G. Domenicucci , John G. Gaudiello , Leon J. Kimball , Jeffrey S. McMurray , Yun-Yu Wang
发明人： Thomas A. Bauer , Steven H. Boettcher , Anthony G. Domenicucci , John G. Gaudiello , Leon J. Kimball , Jeffrey S. McMurray , Yun-Yu Wang
IPC分类号： G01N1/32 , G01N23/04
CPC分类号： G01N1/32 , G01N23/04 , H01J2237/2614
摘要： A method for preparing a transmission electron microscopy (TEM) sample for electron holography includes forming a sacrificial material over an area of interest on the sample, and polishing the sample to a desired thickness, wherein the area of interest is protected from rounding during the polishing. The sacrificial material is removed from the sample following the polishing.
摘要翻译：制备用于电子全息术的透射电子显微镜（TEM）样品的方法包括在样品上的感兴趣区域上形成牺牲材料，并将样品抛光至所需厚度，其中在抛光过程中保护感兴趣区域免于四舍五入。抛光后，从样品中除去牺牲材料。

6. 发明授权

US06380628B2 Microstructure liner having improved adhesion 失效
标题翻译：显微组织衬垫具有改进的粘合性
公开(公告)号：US06380628B2
公开(公告)日：2002-04-30
申请号：US09377329
申请日：1999-08-18
申请人： John A. Miller , Andrew Simon , Jill Slattery , Cyprian E. Uzoh , Yun-Yu Wang
发明人： John A. Miller , Andrew Simon , Jill Slattery , Cyprian E. Uzoh , Yun-Yu Wang
IPC分类号： H01L2348
CPC分类号： H01L21/76862 , H01L21/76816 , H01L21/76843 , H01L21/76865 , H01L21/76871
摘要： A damascene structure, such as a conductive line or via, having a liner with a roughened surface between the substrate and the conductive fill and, preferably, a smooth bottom. The substrate underneath the liner may also have a roughened sidewall and smooth bottom. Such a structure provides enhanced adhesion between one or more layers of the damascene structure. The damascene structure may be manufactured by applying a photoresist over a substrate top surface, exposing the photoresist under conditions that create a standing wave in the resist, and developing the photoresist to provide a pattern having the desired roughened or serrated outline. The pattern is transferred into the substrate, the liner is applied over the substrate bottom and sidewalls, and the liner is filled with conductive material. A roughened liner surface may be achieved by applying a partial layer of liner material over the substrate, removing a portion of the partial layer, and repeating the application and removal steps.
摘要翻译：具有在衬底和导电填料之间具有粗糙表面的衬垫，以及优选光滑底部的镶嵌结构，例如导电线或通孔。衬垫下面的衬底也可以具有粗糙的侧壁和光滑的底部。这种结构提供了镶嵌结构的一层或多层之间增强的附着力。镶嵌结构可以通过在衬底顶表面上施加光致抗蚀剂来制造，在在抗蚀剂中产生驻波的条件下曝光光致抗蚀剂，以及显影光致抗蚀剂以提供具有期望的粗糙化或锯齿形轮廓的图案。将图案转移到衬底中，将衬垫施加在衬底底部和侧壁上，并且衬垫填充有导电材料。可以通过在衬底上施加部分衬里材料层，去除部分层的一部分并重复施加和去除步骤来实现粗糙化衬里表面。

7. 发明授权

US06539625B2 Chromium adhesion layer for copper vias in low-k technology 失效
公开(公告)号：US06539625B2
公开(公告)日：2003-04-01
申请号：US09759017
申请日：2001-01-11
申请人： Brett H. Engel , Mark Hoinkis , John A. Miller , Soon-Cheon Seo , Yun-Yu Wang , Kwong Hon Wong
发明人： Brett H. Engel , Mark Hoinkis , John A. Miller , Soon-Cheon Seo , Yun-Yu Wang , Kwong Hon Wong
IPC分类号： H05K302
CPC分类号： H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Cr, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while maintaining low resistance.

8. 发明授权

US06417567B1 Flat interface for a metal-silicon contract barrier film 失效
标题翻译：金属硅合金阻挡膜的平面接口
公开(公告)号：US06417567B1
公开(公告)日：2002-07-09
申请号：US09482547
申请日：2000-01-13
申请人： Anthony G. Domenicucci , Lynne M. Gignac , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong , Roy A. Carruthers , Christian Lavoie , John A. Miller
发明人： Anthony G. Domenicucci , Lynne M. Gignac , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong , Roy A. Carruthers , Christian Lavoie , John A. Miller
IPC分类号： H01L2348
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/28568 , H01L21/3212 , H01L21/76856 , H01L2221/1078
摘要： A conductive contact having an atomically flat interface. The contact includes, in order, a silicon substrate, a highly disordered silicide layer, and a titanium oxynitride layer. The silicide layer is formed of titanium, silicon, and one of the elements tungsten, tantalum, and molybdenum. The interface between the silicon substrate and the silicide layer is atomically flat. The flat interface prevents diffusion of conductive materials into the underlying silicon substrate. The contact is useful especially for very small devices and shallow junctions, such as are required for ULSI shallow junctions.
摘要翻译：具有原子平坦界面的导电接触。接触依次包括硅衬底，高度无序的硅化物层和氮氧化钛层。硅化物层由钛，硅和元素钨，钽和钼之一形成。硅衬底和硅化物层之间的界面是原子平坦的。平面界面防止导电材料扩散到下面的硅衬底中。该接触对于非常小的器件和浅接头是有用的，例如ULSI浅结点所需的。

9. 发明授权

US06339007B1 Capacitor stack structure and method of fabricating description 失效
标题翻译：电容器堆叠结构及其制造方法
公开(公告)号：US06339007B1
公开(公告)日：2002-01-15
申请号：US09562556
申请日：2000-05-02
申请人： Yun-Yu Wang , Rajarao Jammy , Lee J. Kimball , David E. Kotecki , Jenny Lian , Chenting Lin , John A. Miller , Nicholas Nagel , Hua Shen , Horatio S. Wildman
发明人： Yun-Yu Wang , Rajarao Jammy , Lee J. Kimball , David E. Kotecki , Jenny Lian , Chenting Lin , John A. Miller , Nicholas Nagel , Hua Shen , Horatio S. Wildman
IPC分类号： H01L2120
CPC分类号： H01L28/75 , H01L28/55 , H01L28/60
摘要： A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second insulator portion is provided.
摘要翻译：一种电容器结构，其包括顶部铂电极和在电极的侧壁上具有绝缘体的底部电极，并且其中底部电极从沉积相对于绝缘体在其侧壁上凹进的第一电极部分并且沉积第二绝缘体提供部分。

10. 发明授权

US08368069B2 Antifuse structure for in line circuit modification 有权
公开(公告)号：US08368069B2
公开(公告)日：2013-02-05
申请号：US13360270
申请日：2012-01-27
申请人： Terence L. Kane , Michael P. Tenney , Yun-Yu Wang , Keith Kwong Hon Wong
发明人： Terence L. Kane , Michael P. Tenney , Yun-Yu Wang , Keith Kwong Hon Wong
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L23/5252 , H01L21/76823 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.

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