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1. 发明授权

US06940109B2 High density 3d rail stack arrays and method of making 有权
标题翻译：高密度三维轨道堆叠阵列及其制作方法
公开(公告)号：US06940109B2
公开(公告)日：2005-09-06
申请号：US10779760
申请日：2004-02-18
申请人： Kedar Patel , Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker
发明人： Kedar Patel , Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker
IPC分类号： H01L21/8239 , H01L27/088 , H01L27/092 , H01L27/105 , H01L29/76
CPC分类号： H01L27/088 , H01L27/092 , H01L27/105 , H01L27/1052
摘要： A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.
摘要翻译：半导体器件包括两个晶体管，其中一个晶体管的栅电极和另一个晶体管的源极或漏极位于同一导轨中。单片三维阵列包含多个这样的装置。阵列的不同级别的晶体管优选地具有不同的取向。

2. 发明授权

US06737675B2 High density 3D rail stack arrays 有权
标题翻译：高密度3D轨道堆叠阵列
公开(公告)号：US06737675B2
公开(公告)日：2004-05-18
申请号：US10180046
申请日：2002-06-27
申请人： Kedar Patel , Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker
发明人： Kedar Patel , Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker
IPC分类号： H01L2976
CPC分类号： H01L27/088 , H01L27/092 , H01L27/105 , H01L27/1052
摘要： A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.
摘要翻译：半导体器件包括两个晶体管，其中一个晶体管的栅电极和另一个晶体管的源极或漏极位于同一导轨中。单片三维阵列包含多个这样的装置。阵列的不同级别的晶体管优选地具有不同的取向。

3. 发明授权

US07132335B2 Semiconductor device with localized charge storage dielectric and method of making same 有权
标题翻译：具有局部电荷存储电介质的半导体器件及其制造方法
公开(公告)号：US07132335B2
公开(公告)日：2006-11-07
申请号：US10965763
申请日：2004-10-18
申请人： Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker , Luca Fasoli
发明人： Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker , Luca Fasoli
IPC分类号： H01L21/336
CPC分类号： H01L29/66833 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/792
摘要： An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.
摘要翻译：晶体管阵列包括多个晶体管，沿第一方向延伸的多个字线和沿第二方向延伸的多个位线。每个晶体管包括源极，漏极，沟道和局部电荷存储电介质。所述多个晶体管中的第一晶体管和所述多个晶体管中的第二晶体管共用公共源极/漏极。第一晶体管的第一局部电荷存储电介质不与公共源极/漏极重叠，并且第二晶体管的第二局部电荷存储电介质与公共源极/漏极重叠。

4. 发明授权

US06849905B2 Semiconductor device with localized charge storage dielectric and method of making same 有权
标题翻译：具有局部电荷存储电介质的半导体器件及其制造方法
公开(公告)号：US06849905B2
公开(公告)日：2005-02-01
申请号：US10325951
申请日：2002-12-23
申请人： Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker , Luca Fasoli
发明人： Alper Ilkbahar , Roy Scheuerlein , Andrew J. Walker , Luca Fasoli
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L29/792 , H01L29/72
CPC分类号： H01L29/66833 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/792
摘要： An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.
摘要翻译：晶体管阵列包括多个晶体管，沿第一方向延伸的多个字线和沿第二方向延伸的多个位线。每个晶体管包括源极，漏极，沟道和局部电荷存储电介质。所述多个晶体管中的第一晶体管和所述多个晶体管中的第二晶体管共用公共源极/漏极。第一晶体管的第一局部电荷存储电介质不与公共源极/漏极重叠，并且第二晶体管的第二局部电荷存储电介质与公共源极/漏极重叠。

5. 发明授权

US07433233B2 NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same 有权
标题翻译： NAND存储器阵列结合未选择的存储单元中的沟道区域的电容升压及其操作方法
公开(公告)号：US07433233B2
公开(公告)日：2008-10-07
申请号：US11764793
申请日：2007-06-18
申请人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
发明人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3418 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/115 , H01L27/11568 , H01L27/1159
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

6. 发明授权

US07023739B2 NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same 有权
标题翻译： NAND存储器阵列结合了各个存储单元的多个写脉冲编程及其操作方法
公开(公告)号：US07023739B2
公开(公告)日：2006-04-04
申请号：US10729844
申请日：2003-12-05
申请人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
发明人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0466 , G11C16/0483
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

7. 发明授权

US07233522B2 NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same 有权
标题翻译： NAND存储器阵列结合未选择的存储单元中的沟道区域的电容升压及其操作方法
公开(公告)号：US07233522B2
公开(公告)日：2007-06-19
申请号：US10729831
申请日：2003-12-05
申请人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
发明人： En-Hsing Chen , Andrew J. Walker , Roy E. Scheuerlein , Sucheta Nallamothu , Alper Ilkbahar , Luca G. Fasoli
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C11/5621 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/115 , H01L27/11568 , H01L27/1159
摘要： An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.
摘要翻译：示例性的NAND串存储器阵列提供半选择的存储器单元通道的电容性升压以减少半选择单元的程序干扰效应。为了减小升压电平的漏电流劣化的影响，采用较短持续时间的多个编程脉冲来限制这种漏电流可能降低未选择的NAND串中的电压的时间周期。此外，在每个NAND串的一端或两端的多个串联选择装置进一步确保了对于未选择的和选择的NAND串的这种选择装置的减少的泄漏。在某些示例性实施例中，存储器阵列包括具有电荷存储电介质的存储单元晶体管的串联连接的NAND串，并且包括形成在衬底上方的多于一个的存储单元平面。

8. 发明授权

US07505321B2 Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same 有权
标题翻译：并联串联晶体管串的可编程存储器阵列结构及其制造和操作的方法
公开(公告)号：US07505321B2
公开(公告)日：2009-03-17
申请号：US10335078
申请日：2002-12-31
申请人： Roy E. Scheuerlein , Christopher Petti , Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov
发明人： Roy E. Scheuerlein , Christopher Petti , Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov
IPC分类号： G11C11/34 , G11C16/04 , G11C5/06 , G11C8/00
CPC分类号： H01L27/11568 , G11C11/5621 , G11C16/0483 , H01L27/115 , H01L27/1159
摘要： A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.
摘要翻译：三维闪存阵列包括具有布置在串联连接的NAND串中的电荷存储电介质的薄膜晶体管，以实现4F2存储单元布局。可以仅使用隧穿电流对存储器阵列进行编程和擦除，并且不通过未选择的存储器单元形成泄漏路径。每个NAND串包括用于分别将NAND串的一端耦合到全局位线的两个块选择器件，另一端连接到共享偏置节点。块内的一对NAND串共享相同的全局位线。存储器单元优选地是耗尽型SONOS器件，块选择器件也是如此。存储器单元可以被编程为接近耗尽阈值电压，并且块选择器件保持在具有接近耗尽模式阈值电压的编程状态。多个层上的NAND串可以连接到单个层上的全局位线。通过在每个存储器级别交错NAND串并且每个块使用两个共享偏置节点，对于NAND串的每一端的开关器件需要非常少的附加开销。不同存储器级别的NAND串优选通过垂直堆叠的通孔连接在一起，每个优选地连接到多于一个的存储器级。每个存储器级别可以以每级别少于三个掩码来生成。

9. 发明授权

US07005350B2 Method for fabricating programmable memory array structures incorporating series-connected transistor strings 有权
标题翻译：用于制造并入串联晶体管串的可编程存储器阵列结构的方法
公开(公告)号：US07005350B2
公开(公告)日：2006-02-28
申请号：US10335089
申请日：2002-12-31
申请人： Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Roy E. Scheuerlein , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov , Christopher Petti
发明人： Andrew J. Walker , En-Hsing Chen , Sucheta Nallamothu , Roy E. Scheuerlein , Alper Ilkbahar , Luca Fasoli , Igor Koutnetsov , Christopher Petti
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11502
摘要： A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.
摘要翻译：三维闪存阵列包括具有布置在串联连接的NAND串中的电荷存储电介质的薄膜晶体管，以实现4F 2存储单元布局。可以仅使用隧穿电流对存储器阵列进行编程和擦除，并且不通过未选择的存储器单元形成泄漏路径。每个NAND串包括用于分别将NAND串的一端耦合到全局位线的两个块选择器件，另一端连接到共享偏置节点。块内的一对NAND串共享相同的全局位线。存储器单元优选地是耗尽型SONOS器件，块选择器件也是如此。存储器单元可以被编程为接近耗尽阈值电压，并且块选择器件保持在具有接近耗尽模式阈值电压的编程状态。多个层上的NAND串可以连接到单个层上的全局位线。通过在每个存储器级别交错NAND串并且每个块使用两个共享偏置节点，对于NAND串的每一端的开关器件需要非常少的附加开销。不同存储器级别的NAND串优选通过垂直堆叠的通孔连接在一起，每个优选地连接到多于一个的存储器级。每个存储器级别可以以每级别少于三个掩码来生成。

10. 发明授权

US08278684B1 Voltage protection device 有权
标题翻译：电压保护装置
公开(公告)号：US08278684B1
公开(公告)日：2012-10-02
申请号：US11954514
申请日：2007-12-12
申请人： Andrew J. Walker , Helmut Puchner
发明人： Andrew J. Walker , Helmut Puchner
IPC分类号： H01L29/66
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/0603
摘要： A voltage protection device and method is provided to prevent accidental triggering of an silicon-controlled rectifier (SCR) unless the electrostatic discharge (ESD) is at a predefined threshold above the normal power supply operating voltage or below the ground supply operating voltage. The holding voltage upon the SCR is maintained above the threshold voltage to prevent accidental triggering. The present SCR avoids use of an additional field effect transistor (FET), and avoids relying upon the breakdown of the drain terminal of the FET, but instead programs the amount of holding voltage needed above the power supply voltage using mask-programmability, fuses, or other means for maintaining the holding voltage to a desired range above the power supply voltage. The programmed holding voltage is implemented using a barrier region between the PNP and the NPN of the PNPN junctions of the SCR. In addition to or as an alternative to the barrier region, hole sink junctions can be implemented close to the anode to reduce the substrate resistance in the vicinity of the anode and, therefore, extract holes from their normal target destination.
摘要翻译：提供了一种电压保护装置和方法，以防止硅可控整流器（SCR）的意外触发，除非静电放电（ESD）处于高于正常电源工作电压或低于接地电源工作电压的预定阈值。 SCR上的保持电压保持在阈值电压以上，以防止意外触发。当前的SCR避免使用附加的场效应晶体管（FET），并且避免依赖于FET的漏极端子的击穿，而是使用掩模可编程性，保险丝来编程所需的高于电源电压的保持电压量，或用于将保持电压维持在高于电源电压的期望范围的其它装置。编程的保持电压使用PNP与SCR的PNPN结的NPN之间的屏障区域来实现。除了作为屏障区域的替代方案之外，可以在阳极附近实现空穴接合点，以降低阳极附近的衬底电阻，并因此从其正常目标目的地提取孔。

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