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1. 发明申请

US20120026779A1 NONVOLATILE MEMORIES AND RECONFIGURABLE CIRCUITS 有权
标题翻译：非易失性存储器和可重新配置的电路
公开(公告)号：US20120026779A1
公开(公告)日：2012-02-02
申请号：US13213871
申请日：2011-08-19
申请人： Kazutaka Ikegami , Atsuhiro Kinoshita , Daisuke Hagishima
发明人： Kazutaka Ikegami , Atsuhiro Kinoshita , Daisuke Hagishima
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C2213/72 , G11C2213/77 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/146 , H03K19/1776
摘要： A nonvolatile memory according to an embodiment includes at least one memory cell including: a variable resistance memory comprising one end connected to a first terminal, and the other end connected to a second terminal, a drive voltage being applied to the first terminal; and a diode comprising a cathode connected to the second terminal, and an anode connected to a third terminal, a ground potential being applied to the third terminal. An output of the memory cell is output from the second terminal, the output of the memory cell depends on a resistance state of the variable resistance memory.
摘要翻译：根据实施例的非易失性存储器包括至少一个存储单元，包括：可变电阻存储器，包括连接到第一端子的一端，并且另一端连接到第二端子，施加到第一端子的驱动电压; 以及二极管，包括连接到第二端子的阴极和连接到第三端子的阳极，将地电位施加到第三端子。存储单元的输出从第二端输出，存储单元的输出取决于可变电阻存储器的电阻状态。

2. 发明授权

US08531866B2 Nonvolatile memories and reconfigurable circuits 有权
标题翻译：非易失性存储器和可重新配置电路
公开(公告)号：US08531866B2
公开(公告)日：2013-09-10
申请号：US13213871
申请日：2011-08-19
申请人： Kazutaka Ikegami , Atsuhiro Kinoshita , Daisuke Hagishima
发明人： Kazutaka Ikegami , Atsuhiro Kinoshita , Daisuke Hagishima
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C2213/72 , G11C2213/77 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/146 , H03K19/1776
摘要： A nonvolatile memory according to an embodiment includes at least one memory cell including: a variable resistance memory comprising one end connected to a first terminal, and the other end connected to a second terminal, a drive voltage being applied to the first terminal; and a diode comprising a cathode connected to the second terminal, and an anode connected to a third terminal, a ground potential being applied to the third terminal. An output of the memory cell is output from the second terminal, the output of the memory cell depends on a resistance state of the variable resistance memory.
摘要翻译：根据实施例的非易失性存储器包括至少一个存储单元，包括：可变电阻存储器，包括连接到第一端子的一端，并且另一端连接到第二端子，施加到第一端子的驱动电压; 以及二极管，包括连接到第二端子的阴极和连接到第三端子的阳极，将地电位施加到第三端子。存储单元的输出从第二端输出，存储单元的输出取决于可变电阻存储器的电阻状态。

3. 发明授权

US08525251B2 Nonvolatile programmable logic switch 失效
标题翻译：非易失性可编程逻辑开关
公开(公告)号：US08525251B2
公开(公告)日：2013-09-03
申请号：US13221292
申请日：2011-08-30
申请人： Daisuke Hagishima , Atsuhiro Kinoshita , Kazuya Matsuzawa , Kazutaka Ikegami , Yoshifumi Nishi
发明人： Daisuke Hagishima , Atsuhiro Kinoshita , Kazuya Matsuzawa , Kazutaka Ikegami , Yoshifumi Nishi
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , G11C16/0408 , H01L27/1052 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/11807 , H01L29/66825
摘要： A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the first and second semiconductor regions.
摘要翻译：根据实施例的非易失性可编程逻辑开关包括：存储单元晶体管，包括：在第一导电类型的第一半导体区域中彼此间隔开形成的第二导电类型的第一源极区域和第一漏极区域; 第一绝缘膜，电荷存储膜，第二绝缘膜和控制栅极，并且形成在第一源极区域和第一漏极区域之间的第一半导体区域上; 传输晶体管，包括：在第一导电类型的第二半导体区域中彼此成一定距离地形成的第二导电类型的第二源极区域和第二漏极区域; 第三绝缘膜，栅极电极，并且形成在第二源极区域和第二漏极区域之间的第二半导体区域上，栅极电连接到第一漏极区域; 以及用于将衬底偏压施加到第一和第二半导体区域的电极。

4. 发明授权

US08476690B2 Nonvolatile programmable logic switches and semiconductor integrated circuit 失效
标题翻译：非易失性可编程逻辑开关和半导体集成电路
公开(公告)号：US08476690B2
公开(公告)日：2013-07-02
申请号：US13223331
申请日：2011-09-01
申请人： Daisuke Hagishima , Atsuhiro Kinoshita
发明人： Daisuke Hagishima , Atsuhiro Kinoshita
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： H01L29/788 , G11C16/0416 , G11C16/0466 , H01L27/11521 , H01L27/11526 , H01L27/11534 , H01L27/11807
摘要： A nonvolatile programmable logic switch according to an embodiment includes: a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type; a memory cell transistor including a first insulating film formed on the first semiconductor region, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control gate formed on the second insulating film; a pass transistor including a third insulating film formed on the second semiconductor region, and a gate electrode formed on the third insulating film and electrically connected to the first drain region; a first electrode applying a substrate bias to the first semiconductor region, the first electrode being formed in the first semiconductor region; and a second electrode applying a substrate bias to the second semiconductor region, the second electrode being formed in the second semiconductor region.
摘要翻译：根据实施例的非易失性可编程逻辑开关包括：第一导电类型的第一半导体区域和第二导电类型的第二半导体区域; 存储单元晶体管，包括形成在第一半导体区域上的第一绝缘膜，形成在第一绝缘膜上的电荷存储膜，形成在电荷存储膜上的第二绝缘膜，以及形成在第二绝缘膜上的控制栅; 包括形成在第二半导体区域上的第三绝缘膜的通过晶体管和形成在第三绝缘膜上并电连接到第一漏极区的栅电极; 将第一电极施加到所述第一半导体区域的衬底偏压，所述第一电极形成在所述第一半导体区域中; 以及向所述第二半导体区域施加衬底偏压的第二电极，所述第二电极形成在所述第二半导体区域中。

5. 发明申请

US20060214217A1 Nonvolatile semiconductor storage device and manufacturing method therefor 失效
公开(公告)号：US20060214217A1
公开(公告)日：2006-09-28
申请号：US11224049
申请日：2005-09-13
申请人： Hiroshi Watanabe , Atsuhiro Kinoshita , Akira Takashima , Daisuke Hagishima
发明人： Hiroshi Watanabe , Atsuhiro Kinoshita , Akira Takashima , Daisuke Hagishima
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A nonvolatile semiconductor storage device includes a semiconductor substrate; a plurality of isolation regions formed in the semiconductor substrate; an element-forming region formed between adjacent isolation regions; a first gate insulating film provided on the element-forming region; a floating gate electrode which is provided on the first gate insulating film and in which a width of a lower hem facing the element-forming region is narrower than a width of the element-forming region in a section taken in a direction perpendicular to a direction in which the isolation regions extend; a second gate insulating film provided on the floating gate electrode; and a control gate electrode provided on the second gate insulating film.

6. 发明申请

US20120139030A1 NONVOLATILE SEMICONDUCTOR MEMORY 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US20120139030A1
公开(公告)日：2012-06-07
申请号：US13316603
申请日：2011-12-12
申请人： Kiwamu SAKUMA , Atsuhiro Kinoshita , Masahiro Kiyotoshi , Daisuke Hagishima , Koichi Muraoka
发明人： Kiwamu SAKUMA , Atsuhiro Kinoshita , Masahiro Kiyotoshi , Daisuke Hagishima , Koichi Muraoka
IPC分类号： H01L27/105 , H01L21/8239
CPC分类号： H01L29/42328 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.
摘要翻译：根据一个实施例，非易失性半导体存储器包括在第一方向上的第一至第n（n是不小于2的自然数）半导体层，并且在第二方向上延伸，并且半导体层具有阶梯状图案第二方向的第一端，在第二方向的第一端中共同连接到第一至第n半导体层的公共半导体层，第一至第n层选择晶体管，其从第一电极侧第一电极和第一至第n存储器串以及使第i层选择晶体管（i为1至n之一）的第一至第n杂质区在第一端中的正常导通状态第i个半导体层的第2方向。

7. 发明申请

US20120061731A1 NONVOLATILE PROGRAMMABLE LOGIC SWITCHES AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：非易失性可编程逻辑开关和半导体集成电路
公开(公告)号：US20120061731A1
公开(公告)日：2012-03-15
申请号：US13223331
申请日：2011-09-01
申请人： Daisuke Hagishima , Atsuhiro Kinoshita
发明人： Daisuke Hagishima , Atsuhiro Kinoshita
IPC分类号： H01L27/092
CPC分类号： H01L29/788 , G11C16/0416 , G11C16/0466 , H01L27/11521 , H01L27/11526 , H01L27/11534 , H01L27/11807
摘要： A nonvolatile programmable logic switch according to an embodiment includes: a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type; a memory cell transistor including a first insulating film formed on the first semiconductor region, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control gate formed on the second insulating film; a pass transistor including a third insulating film formed on the second semiconductor region, and a gate electrode formed on the third insulating film and electrically connected to the first drain region; a first electrode applying a substrate bias to the first semiconductor region, the first electrode being formed in the first semiconductor region; and a second electrode applying a substrate bias to the second semiconductor region, the second electrode being formed in the second semiconductor region.
摘要翻译：根据实施例的非易失性可编程逻辑开关包括：第一导电类型的第一半导体区域和第二导电类型的第二半导体区域; 存储单元晶体管，包括形成在第一半导体区域上的第一绝缘膜，形成在第一绝缘膜上的电荷存储膜，形成在电荷存储膜上的第二绝缘膜，以及形成在第二绝缘膜上的控制栅; 包括形成在第二半导体区域上的第三绝缘膜的通过晶体管和形成在第三绝缘膜上并电连接到第一漏极区的栅电极; 将第一电极施加到所述第一半导体区域的衬底偏压，所述第一电极形成在所述第一半导体区域中; 以及向所述第二半导体区域施加衬底偏压的第二电极，所述第二电极形成在所述第二半导体区域中。

8. 发明授权

US07977729B2 Aging device 有权
标题翻译：老化设备
公开(公告)号：US07977729B2
公开(公告)日：2011-07-12
申请号：US12173535
申请日：2008-07-15
申请人： Hiroshi Watanabe , Atsuhiro Kinoshita , Shigeki Kobayashi , Daisuke Hagishima
发明人： Hiroshi Watanabe , Atsuhiro Kinoshita , Shigeki Kobayashi , Daisuke Hagishima
IPC分类号： H01L29/788
CPC分类号： G04F10/10 , G11C16/0408 , G11C2216/10 , H01L21/28273 , H01L27/115 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： An aging device according to an embodiment of the present invention includes a semiconductor substrate, first and second diffusion layers provided in a first element region, a floating gate provided above a channel region between the first and second diffusion layers, and a control gate electrode provided beside the floating gate with an interval in the lateral direction. A coupling capacitance between the floating gate and the control gate electrode is larger than a coupling capacitance between the floating gate and the semiconductor substrate.
摘要翻译：根据本发明的实施例的老化装置包括半导体衬底，设置在第一元件区域中的第一和第二扩散层，设置在第一和第二扩散层之间的沟道区域上方的浮动栅极和设置在第一和第二扩散层之间的控制栅电极在浮动门旁边，横向间隔一段距离。浮置栅极和控制栅电极之间的耦合电容大于浮置栅极和半导体衬底之间的耦合电容。

9. 发明授权

US08779502B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US08779502B2
公开(公告)日：2014-07-15
申请号：US13316603
申请日：2011-12-12
申请人： Kiwamu Sakuma , Atsuhiro Kinoshita , Masahiro Kiyotoshi , Daisuke Hagishima , Koichi Muraoka
发明人： Kiwamu Sakuma , Atsuhiro Kinoshita , Masahiro Kiyotoshi , Daisuke Hagishima , Koichi Muraoka
IPC分类号： H01L29/792 , H01L29/66 , H01L21/70 , H01L21/336
CPC分类号： H01L29/42328 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.
摘要翻译：根据一个实施例，非易失性半导体存储器包括在第一方向上的第一至第n（n是不小于2的自然数）半导体层，并且在第二方向上延伸，并且半导体层具有阶梯状图案第二方向的第一端，在第二方向的第一端中共同连接到第一至第n半导体层的公共半导体层，第一至第n层选择晶体管，其从第一电极侧第一电极和第一至第n存储器串以及使第i层选择晶体管（i为1至n之一）的第一至第n杂质区在第一端中的正常导通状态第i个半导体层的第2方向。

10. 发明授权

US08553464B2 Nonvolatile programmable logic switch 有权
标题翻译：非易失性可编程逻辑开关
公开(公告)号：US08553464B2
公开(公告)日：2013-10-08
申请号：US13240087
申请日：2011-09-22
申请人： Yoshifumi Nishi , Daisuke Hagishima , Shinichi Yasuda , Tetsufumi Tanamoto , Takahiro Kurita , Atsuhiro Kinoshita , Shinobu Fujita
发明人： Yoshifumi Nishi , Daisuke Hagishima , Shinichi Yasuda , Tetsufumi Tanamoto , Takahiro Kurita , Atsuhiro Kinoshita , Shinobu Fujita
IPC分类号： G11C11/35
CPC分类号： H01L27/11568 , G11C16/0458 , G11C16/10 , H01L27/11573 , H01L27/11803
摘要： An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.
摘要翻译：本实施例的一个方面提供了一种非易失性可编程逻辑开关，包括第一存储单元晶体管，第二存储单元晶体管，传输晶体管和向该通过晶体管施加衬底电压的第一衬底电极，其中写入电压为施加到第一布线，第一电压施加到第二布线和第三布线中的一个，并且低于第一电压的第二电压施加到第二布线和第三布线中的另一布线，第一基板当数据被写入第一存储单元晶体管或第二存储单元晶体管时，高于第二电压并低于第一电压的电压被施加到传输晶体管的阱。

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