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1. 发明授权

US08779502B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US08779502B2
公开(公告)日：2014-07-15
申请号：US13316603
申请日：2011-12-12
申请人： Kiwamu Sakuma , Atsuhiro Kinoshita , Masahiro Kiyotoshi , Daisuke Hagishima , Koichi Muraoka
发明人： Kiwamu Sakuma , Atsuhiro Kinoshita , Masahiro Kiyotoshi , Daisuke Hagishima , Koichi Muraoka
IPC分类号： H01L29/792 , H01L29/66 , H01L21/70 , H01L21/336
CPC分类号： H01L29/42328 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.
摘要翻译：根据一个实施例，非易失性半导体存储器包括在第一方向上的第一至第n（n是不小于2的自然数）半导体层，并且在第二方向上延伸，并且半导体层具有阶梯状图案第二方向的第一端，在第二方向的第一端中共同连接到第一至第n半导体层的公共半导体层，第一至第n层选择晶体管，其从第一电极侧第一电极和第一至第n存储器串以及使第i层选择晶体管（i为1至n之一）的第一至第n杂质区在第一端中的正常导通状态第i个半导体层的第2方向。

2. 发明申请

US20110049611A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 审中-公开
标题翻译：非挥发性半导体存储器件的非线性半导体存储器件的制造方法和非易失性半导体存储器件的制造方法
公开(公告)号：US20110049611A1
公开(公告)日：2011-03-03
申请号：US12769951
申请日：2010-04-29
申请人： Masahiro Kiyotoshi , Atsuhiro Kinoshita , Kiwamu Sakuma , Koichi Muraoka , Ichiro Mizushima
发明人： Masahiro Kiyotoshi , Atsuhiro Kinoshita , Kiwamu Sakuma , Koichi Muraoka , Ichiro Mizushima
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L27/11526 , H01L27/11529 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881
摘要： In a memory cell portion, a stacked structure, in which dielectric layers and semiconductor layers are alternately stacked, is arranged in a fin shape on a semiconductor substrate, and in a peripheral circuit portion, a gate electrode is arranged on the semiconductor substrate via a gate dielectric film so that a height of an upper surface of the gate electrode is set to be substantially equal to a height of an upper surface of the stacked structure in which the dielectric layers and the semiconductor layers are alternately stacked.
摘要翻译：在存储单元部分中，电介质层和半导体层交替层叠的堆叠结构在半导体衬底上以翅片形状布置，并且在外围电路部分中，栅电极经由使得栅极电极的上表面的高度被设定为与电介质层和半导体层交替层叠的层叠结构的上表面的高度大致相等。

3. 发明授权

US09076722B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US09076722B2
公开(公告)日：2015-07-07
申请号：US13547567
申请日：2012-07-12
申请人： Kiwamu Sakuma , Masahiro Kiyotoshi , Atsuhiro Kinoshita , Haruka Kusai
发明人： Kiwamu Sakuma , Masahiro Kiyotoshi , Atsuhiro Kinoshita , Haruka Kusai
IPC分类号： H01L29/76 , H01L29/788 , H01L29/66 , H01L29/792 , H01L27/24 , H01L21/8234 , H01L27/115 , H01L27/22 , H01L21/84 , H01L27/12 , H01L27/06
CPC分类号： H01L45/1233 , H01L21/823431 , H01L21/845 , H01L27/0688 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L27/1211 , H01L27/222 , H01L27/2454 , H01L27/2481 , H01L29/7881 , H01L29/792 , H01L45/1206 , H01L45/1253
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括鳍式堆叠层结构。每个结构包括沿垂直方向堆叠的半导体层。辅助栅电极沿面内方向设置，并在结构垂直方向的一个表面上划分。

4. 发明申请

US20130069134A1 MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES 失效
标题翻译：包含两个浮动门结构的晶体管的存储器
公开(公告)号：US20130069134A1
公开(公告)日：2013-03-21
申请号：US13608436
申请日：2012-09-10
申请人： Tetsufumi TANAMOTO , Kosuke Tatsumura , Kiwamu Sakuma , Atsuhiro Kinoshita , Shinobu Fujita , Koichi Muraoka
发明人： Tetsufumi TANAMOTO , Kosuke Tatsumura , Kiwamu Sakuma , Atsuhiro Kinoshita , Shinobu Fujita , Koichi Muraoka
IPC分类号： H01L27/11
CPC分类号： H01L29/42332 , G11C11/412 , G11C14/0063 , H01L27/1104 , H01L29/7881
摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.
摘要翻译：在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极，第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜，第四浮栅，第六绝缘膜和第二控制栅极。

5. 发明授权

US08610196B2 Memory including transistors with double floating gate structures 失效
标题翻译：存储器包括具有双浮栅结构的晶体管
公开(公告)号：US08610196B2
公开(公告)日：2013-12-17
申请号：US13608436
申请日：2012-09-10
申请人： Tetsufumi Tanamoto , Kosuke Tatsumura , Kiwamu Sakuma , Atsuhiro Kinoshita , Shinobu Fujita , Koichi Muraoka
发明人： Tetsufumi Tanamoto , Kosuke Tatsumura , Kiwamu Sakuma , Atsuhiro Kinoshita , Shinobu Fujita , Koichi Muraoka
IPC分类号： H01L27/11
CPC分类号： H01L29/42332 , G11C11/412 , G11C14/0063 , H01L27/1104 , H01L29/7881
摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.
摘要翻译：在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极，第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜，第四浮栅，第六绝缘膜和第二控制栅极。

6. 发明授权

US08546872B2 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08546872B2
公开(公告)日：2013-10-01
申请号：US13072366
申请日：2011-03-25
申请人： Kiwamu Sakuma , Atsuhiro Kinoshita
发明人： Kiwamu Sakuma , Atsuhiro Kinoshita
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11524 , H01L27/11551 , H01L29/7881
摘要： According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other.
摘要翻译：根据一个实施例，存储器件包括半导体衬底，第一，第二，第三和第四鳍式堆叠层结构，每个具有堆叠在垂直于半导体衬底的表面的第一方向上的存储串，并且每个延伸到第二方向平行于半导体衬底的表面，第一部分连接到第一和第二鳍式堆叠层的第二方向上的第一端彼此结合，第二部分连接到第三端的第二端第四鳍状堆叠层结构，第三部分与第一和第三鳍状堆叠层的第二方向的第二端部连接，第四部分与第二鳍片状堆叠层的第二方向的第二端部连接，第二和第四鳍式堆叠层结构。

7. 发明授权

US08513725B2 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08513725B2
公开(公告)日：2013-08-20
申请号：US13236734
申请日：2011-09-20
申请人： Kiwamu Sakuma , Atsuhiro Kinoshita
发明人： Kiwamu Sakuma , Atsuhiro Kinoshita
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L27/11578 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L29/785 , H01L29/792
摘要： According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.
摘要翻译：根据一个实施例，存储器件包括第一和第二鳍式堆叠结构，每个第一和第二鳍式堆叠结构每个包括沿第一方向堆叠的第一至第i存储器串（i是除1之外的自然数），第一和第二鳍式堆叠结构其在第二方向上延伸并且在第三方向上相邻，第一部分连接到第一鳍式堆叠结构的第二方向上的一端，第一部分的第三方向上的宽度大于第一方向上的宽度第一鳍式堆叠结构的第三方向和与第二鳍式堆叠结构的第二方向的一端连接的第二部分，第二部分的第三方向上的宽度大于第三方向上的宽度的第二鳍式堆叠结构。

8. 发明申请

US20130015519A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20130015519A1
公开(公告)日：2013-01-17
申请号：US13622612
申请日：2012-09-19
申请人： Shosuke Fujii , Kiwamu Sakuma , Jun Fujiki , Atsuhiro Kinoshita
发明人： Shosuke Fujii , Kiwamu Sakuma , Jun Fujiki , Atsuhiro Kinoshita
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/11551 , H01L27/11519 , H01L27/11521 , H01L27/11565 , H01L27/11578
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes first to n-th semiconductor layers which are stacked in a first direction perpendicular to a surface of a semiconductor substrate and which extend in a second direction parallel to the surface of the semiconductor substrate, an electrode which extends in the first direction along side surfaces of the first to n-th semiconductor layers, the side surfaces of the first to n-th semiconductor layers exposing in a third direction perpendicular to the first and second directions, and first to n-th charge storage layers located between the first to n-th semiconductor layers and the electrode respectively. The first to n-th charge storage layers are separated from each other in areas between the first to n-th semiconductor layers.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括第一至第n半导体层，它们沿垂直于半导体衬底的表面的第一方向堆叠并且沿与半导体衬底的表面平行的第二方向延伸，电极，其沿第一方向沿着第一至第n半导体层的侧表面延伸，第一至第n半导体层的侧表面在垂直于第一和第二方向的第三方向上暴露，以及第一至第n- 分别位于第一至第n半导体层之间的电荷存储层和电极。第一至第n电荷存储层在第一至第n半导体层之间的区域中彼此分离。

9. 发明授权

US09087715B2 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US09087715B2
公开(公告)日：2015-07-21
申请号：US13547645
申请日：2012-07-12
申请人： Haruka Kusai , Kiwamu Sakuma , Shosuke Fujii , Masumi Saitoh , Masahiro Kiyotoshi
发明人： Haruka Kusai , Kiwamu Sakuma , Shosuke Fujii , Masumi Saitoh , Masahiro Kiyotoshi
IPC分类号： H01L27/115 , H01L27/088 , H01L21/265 , H01L21/02 , H01L21/3205 , H01L21/768 , H01L27/24 , G11C16/04 , H01L29/66 , H01L29/68 , H01L29/788 , H01L29/792 , G11C16/10 , H01L29/82
CPC分类号： H01L27/088 , G11C16/04 , G11C16/10 , H01L21/02367 , H01L21/265 , H01L21/32051 , H01L21/76877 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/685 , H01L29/788 , H01L29/792 , H01L29/82
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括具有存储单元的鳍式堆叠层结构和连接到该结构的端部的光束。结构和梁中的每一个包括沿垂直方向堆叠的半导体层。梁包括设置在梁的一端的接触部分和设置在接触部分和结构的端部之间的低电阻部分。

10. 发明申请

US20130175490A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20130175490A1
公开(公告)日：2013-07-11
申请号：US13547645
申请日：2012-07-12
申请人： Haruka KUSAI , Kiwamu Sakuma , Shosuke Fujii , Masumi Saitoh , Masahiro Kiyotoshi
发明人： Haruka KUSAI , Kiwamu Sakuma , Shosuke Fujii , Masumi Saitoh , Masahiro Kiyotoshi
IPC分类号： H01L27/088 , H01L27/24 , H01L21/3205 , H01L21/768 , H01L21/265 , H01L21/02
CPC分类号： H01L27/088 , G11C16/04 , G11C16/10 , H01L21/02367 , H01L21/265 , H01L21/32051 , H01L21/76877 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/685 , H01L29/788 , H01L29/792 , H01L29/82
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括具有存储单元的鳍式堆叠层结构和连接到该结构的端部的光束。结构和梁中的每一个包括沿垂直方向堆叠的半导体层。梁包括设置在梁的一端的接触部分和设置在接触部分和结构的端部之间的低电阻部分。

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