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1. 发明授权

US08238182B2 Semiconductor device and data processing system comprising semiconductor device 失效
公开(公告)号：US08238182B2
公开(公告)日：2012-08-07
申请号：US12881750
申请日：2010-09-14
申请人： Soichiro Yoshida , Kazuhiko Kajigaya , Yasutoshi Yamada
发明人： Soichiro Yoshida , Kazuhiko Kajigaya , Yasutoshi Yamada
IPC分类号： G11C7/06
CPC分类号： G11C11/4096 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C11/4091 , G11C11/4097 , G11C2207/002
摘要： A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof.

2. 发明申请

US20110248697A1 Semiconductor device and data processing system 审中-公开
标题翻译：半导体器件和数据处理系统
公开(公告)号：US20110248697A1
公开(公告)日：2011-10-13
申请号：US13064683
申请日：2011-04-08
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Yasutoshi Yamada
IPC分类号： G05F3/08
CPC分类号： G11C5/147 , G11C7/04 , G11C11/4091
摘要： A semiconductor device comprises a first circuit outputting a signal to a first signal line, a first FET applied with a driving signal and having a gate electrode connected to a first node, a second FET controlling an electrical connection between the first signal line and the first node, a third FET amplifying a signal of the first node, a second circuit precharging the first signal line, and a voltage control circuit. A gate capacitance of the first FET is controlled in response to a voltage difference between the first node and the driving signal. The voltage control circuit shifts a potential of the driving signal when the second FET is non-conductive after the signal of the first-circuit is transmitted to the first node, and performs an offset control for the driving signal so as to compensate a variation of a threshold voltage of the first FET.
摘要翻译：半导体器件包括将信号输出到第一信号线的第一电路，施加有驱动信号的第一FET并具有连接到第一节点的栅极;第二FET控制第一信号线与第一信号线之间的电连接放大第一节点的信号的第三FET，对第一信号线预充电的第二电路和电压控制电路。响应于第一节点和驱动信号之间的电压差来控制第一FET的栅极电容。在第一电路的信号被发送到第一节点之后，当第二FET不导通时，电压控制电路移动驱动信号的电位，并且对驱动信号进行偏移控制，以补偿第一FET的阈值电压。

3. 发明授权

US07933141B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07933141B2
公开(公告)日：2011-04-26
申请号：US12416432
申请日：2009-04-01
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24
CPC分类号： G11C5/147 , G11C7/04 , G11C11/4076 , G11C11/4091 , G11C11/4097
摘要： In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.
摘要翻译：在半导体存储器件中，存储单元通过局部位线和全局位线与本地读出放大器和全局读出放大器连接。本地读出放大器是包括单个MOS晶体管的单端读出放大器，其检测当与存储单元读取和写入数据时变化的局部位线的电位。监视MOS晶体管的阈值电压，以产生高电平写入电压和低电平写入电压，这些电压根据监视结果进行校正和移位，从而通过以下方式适当地执行对存储器单元的重新加载操作：全局局部感测放大器。因此，可以消除阈值电压的温度变化和由于制造工艺的分散造成的阈值电压的偏移。

4. 发明授权

US07903449B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07903449B2
公开(公告)日：2011-03-08
申请号：US12485568
申请日：2009-06-16
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24
CPC分类号： G11C7/02 , G11C11/4074 , G11C11/4099 , H01L27/0207 , H01L27/0688 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/91
摘要： A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise.
摘要翻译：半导体存储器件（例如DRAM）由包括多个存储单元，多个字线驱动器，多个读出放大器和多个虚拟电容器的存储单元阵列构成。每个存储单元包括晶体管和电容器，位于字线和位线之间的交点处。电容器的第一电极连接到存储单元中的晶体管。虚拟电容器的第一电极连接在一起并被提供第二电位（例如VDD或VSS）。虚拟电容器的第二电极与存储单元的电容器的第二电极连接在一起并被提供有第一电位（例如VPL）。虚拟电容器用作板电压VPL的平滑电容，以减少板噪声。

5. 发明授权

US08988958B2 Sense amplifier circuit and semiconductor device 有权
公开(公告)号：US08988958B2
公开(公告)日：2015-03-24
申请号：US14306293
申请日：2014-06-17
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Yasutoshi Yamada
IPC分类号： G11C7/00 , G11C7/06 , G11C11/4091 , G11C5/14 , G11C7/10
CPC分类号： G11C7/06 , G11C5/147 , G11C7/065 , G11C7/067 , G11C7/1087 , G11C11/4091
摘要： A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

6. 发明申请

US20100054066A1 Memory device, semiconductor memory device and control method thereof 有权
标题翻译：存储器件，半导体存储器件及其控制方法
公开(公告)号：US20100054066A1
公开(公告)日：2010-03-04
申请号：US12461770
申请日：2009-08-24
申请人： Kazuhiko Kajigaya , Soichiro Yoshida
发明人： Kazuhiko Kajigaya , Soichiro Yoshida
IPC分类号： G11C7/02 , G11C7/00 , G11C8/08
CPC分类号： G11C7/00 , G11C7/02 , G11C7/12 , G11C8/08 , G11C11/4076 , G11C11/4091 , G11C11/4097
摘要： A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit line is selectively connected to the first bit line via the first sense amplifier. A signal voltage decision unit in the second sense amplifier determines the signal level of the second bit line being supplied with the output current. The sense amplifier control circuit controls connection between the amplifying element and the unit in accordance with a determination timing, which switches the above connection from a connected state to a disconnected state at a first timing in a normal operation and switches in the same manner at a delayed second timing in a refresh operation.
摘要翻译：半导体存储器件包括存储单元阵列，第一和第二位线，第一和第二放大器以及读出放大器控制电路。第一读出放大器中的放大元件放大第一位线的信号并将其转换为输出电流。第二位线经由第一读出放大器选择性地连接到第一位线。第二读出放大器中的信号电压判定单元确定被提供有输出电流的第二位线的信号电平。读出放大器控制电路根据在正常操作中的第一定时将上述连接从连接状态切换到断开状态的确定定时来控制放大元件与单元之间的连接，并以相同的方式在一个在刷新操作中延迟第二定时。

7. 发明申请

US20090257298A1 Semiconductor device having single-ended sensing amplifier 有权
标题翻译：具有单端感测放大器的半导体器件
公开(公告)号：US20090257298A1
公开(公告)日：2009-10-15
申请号：US12382494
申请日：2009-03-17
申请人： Kazuhiko Kajigaya , Soichiro Yoshida
发明人： Kazuhiko Kajigaya , Soichiro Yoshida
IPC分类号： G11C7/02 , G11C7/00 , G11C11/22
CPC分类号： G11C8/08 , G11C7/067 , G11C11/22 , G11C11/223 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004
摘要： A single-ended sense amplifier in a semiconductor storage device having a hierarchical bit line structure includes a first MOS transistor for amplifying a signal outputted from a memory cell to a bit line, a second MOS transistor for feeding the output of the first MOS transistor to a global bit line, and a global bit line voltage determination circuit; and at least the ON/OFF timing of the second MOS transistor or the read timing of a global sense amplifier that includes the global bit line voltage determination circuit is controlled by the output signal of a delay circuit that includes a replica of the first MOS transistor and a replica of the global bit line voltage determination circuit.
摘要翻译：具有分层位线结构的半导体存储装置中的单端读出放大器包括：第一MOS晶体管，用于将从存储单元输出的信号放大到位线;第二MOS晶体管，用于将第一MOS晶体管的输出馈送到全局位线和全局位线电压确定电路; 并且包括全局位线电压确定电路的至少第二MOS晶体管的ON / OFF定时或包括全局位线电压确定电路的全局读出放大器的读取定时由包括第一MOS晶体管的复制品的延迟电路的输出信号控制以及全局位线电压确定电路的副本。

8. 发明申请

US20090251948A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090251948A1
公开(公告)日：2009-10-08
申请号：US12416432
申请日：2009-04-01
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24 , G11C7/06 , G11C7/00
CPC分类号： G11C5/147 , G11C7/04 , G11C11/4076 , G11C11/4091 , G11C11/4097
摘要： In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.
摘要翻译：在半导体存储器件中，存储单元通过局部位线和全局位线与本地读出放大器和全局读出放大器连接。本地读出放大器是包括单个MOS晶体管的单端读出放大器，其检测当与存储单元读取和写入数据时变化的局部位线的电位。监视MOS晶体管的阈值电压，以产生高电平写入电压和低电平写入电压，这些电压根据监视结果进行校正和移位，从而通过对存储器单元适当地执行重新加载操作全局局部感测放大器。因此，可以消除阈值电压的温度变化和由于制造工艺的分散造成的阈值电压的偏移。

9. 发明授权

US08355289B2 Memory device, semiconductor memory device and control method thereof 有权
公开(公告)号：US08355289B2
公开(公告)日：2013-01-15
申请号：US12461770
申请日：2009-08-24
申请人： Kazuhiko Kajigaya , Soichiro Yoshida
发明人： Kazuhiko Kajigaya , Soichiro Yoshida
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/02 , G11C7/12 , G11C8/08 , G11C11/4076 , G11C11/4091 , G11C11/4097
摘要： A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit line is selectively connected to the first bit line via the first sense amplifier. A signal voltage decision unit in the second sense amplifier determines the signal level of the second bit line being supplied with the output current. The sense amplifier control circuit controls connection between the amplifying element and the unit in accordance with a determination timing, which switches the above connection from a connected state to a disconnected state at a first timing in a normal operation and switches in the same manner at a delayed second timing in a refresh operation.

10. 发明授权

US08320208B2 Sense amplifier circuit and semiconductor device 有权
标题翻译：感应放大器电路和半导体器件
公开(公告)号：US08320208B2
公开(公告)日：2012-11-27
申请号：US12882789
申请日：2010-09-15
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Yasutoshi Yamada
IPC分类号： G11C7/02 , G11C7/00
CPC分类号： G11C7/06 , G11C5/147 , G11C7/065 , G11C7/067 , G11C7/1087 , G11C11/4091
摘要： A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.
摘要翻译：本发明的单端读出放大器电路包括第一和第二MOS晶体管以及第一和第二预充电电路。第一MOS晶体管将位线驱动到预定电压并且切换位线和感测节点之间的连接，并且栅极连接到感测节点的第二MOS晶体管经由第一MOS晶体管放大信号。第一预充电电路将位线预充电到第一电位，而第二预充电电路将感测节点预充电到第二电位。在感测操作之前，当控制上述栅极电压降低时，位线被驱动到预定电压。适当地设定预定电压，使得可以在电荷转移/分配模式之间的变化点附近获得在高电平和低电平之间的感测节点处的所需电压差。

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