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1. 发明申请

US20140293721A1 SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE 有权
标题翻译： SENSE放大器电路和半导体器件
公开(公告)号：US20140293721A1
公开(公告)日：2014-10-02
申请号：US14306293
申请日：2014-06-17
申请人： Kazuhiko KAJIGAYA , Soichiro YOSHIDA , Yasutoshi YAMADA
发明人： Kazuhiko KAJIGAYA , Soichiro YOSHIDA , Yasutoshi YAMADA
IPC分类号： G11C11/4091
CPC分类号： G11C7/06 , G11C5/147 , G11C7/065 , G11C7/067 , G11C7/1087 , G11C11/4091
摘要： A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.
摘要翻译：本发明的单端读出放大器电路包括第一和第二MOS晶体管以及第一和第二预充电电路。第一MOS晶体管将位线驱动到预定电压并且切换位线和感测节点之间的连接，并且栅极连接到感测节点的第二MOS晶体管经由第一MOS晶体管放大信号。第一预充电电路将位线预充电到第一电位，而第二预充电电路将感测节点预充电到第二电位。在感测操作之前，当控制上述栅极电压降低时，位线被驱动到预定电压。适当地设定预定电压，使得可以在电荷转移/分配模式之间的变化点附近获得在高电平和低电平之间的感测节点处的所需电压差。

2. 发明申请

US20110261631A1 SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR DEVICE 失效
标题翻译：包含半导体器件的半导体器件和数据处理系统
公开(公告)号：US20110261631A1
公开(公告)日：2011-10-27
申请号：US13174888
申请日：2011-07-01
申请人： Soichiro YOSHIDA , Kazuhiko KAJIGAYA , Yasutoshi YAMADA
发明人： Soichiro YOSHIDA , Kazuhiko KAJIGAYA , Yasutoshi YAMADA
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/1048 , G11C7/02 , G11C7/1051 , G11C7/1069 , G11C11/4091 , G11C11/4096 , G11C11/4097 , G11C2207/002
摘要： A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof.
摘要翻译：半导体器件包括放大通过位线传输的信号的读出放大器电路，传输由读出放大器电路放大的信号的第一/第二数据线，由第一电压驱动并放大该信号的读取放大器电路; 控制上述部件之间的连接的第一/第二开关电路，将第二/第三数据线设置为低于第一电压的第二电压的第一/第二电压设置电路。通过将第二电压加到第二/第三开关电路中的晶体管的阈值电压而获得的预定电压被施加到其栅极端，并且数据线的端部连接到其源极和漏极端子。

3. 发明授权

US07933141B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07933141B2
公开(公告)日：2011-04-26
申请号：US12416432
申请日：2009-04-01
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24
CPC分类号： G11C5/147 , G11C7/04 , G11C11/4076 , G11C11/4091 , G11C11/4097
摘要： In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.
摘要翻译：在半导体存储器件中，存储单元通过局部位线和全局位线与本地读出放大器和全局读出放大器连接。本地读出放大器是包括单个MOS晶体管的单端读出放大器，其检测当与存储单元读取和写入数据时变化的局部位线的电位。监视MOS晶体管的阈值电压，以产生高电平写入电压和低电平写入电压，这些电压根据监视结果进行校正和移位，从而通过以下方式适当地执行对存储器单元的重新加载操作：全局局部感测放大器。因此，可以消除阈值电压的温度变化和由于制造工艺的分散造成的阈值电压的偏移。

4. 发明授权

US07903449B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07903449B2
公开(公告)日：2011-03-08
申请号：US12485568
申请日：2009-06-16
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24
CPC分类号： G11C7/02 , G11C11/4074 , G11C11/4099 , H01L27/0207 , H01L27/0688 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/91
摘要： A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise.
摘要翻译：半导体存储器件（例如DRAM）由包括多个存储单元，多个字线驱动器，多个读出放大器和多个虚拟电容器的存储单元阵列构成。每个存储单元包括晶体管和电容器，位于字线和位线之间的交点处。电容器的第一电极连接到存储单元中的晶体管。虚拟电容器的第一电极连接在一起并被提供第二电位（例如VDD或VSS）。虚拟电容器的第二电极与存储单元的电容器的第二电极连接在一起并被提供有第一电位（例如VPL）。虚拟电容器用作板电压VPL的平滑电容，以减少板噪声。

5. 发明申请

US20090323399A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090323399A1
公开(公告)日：2009-12-31
申请号：US12485568
申请日：2009-06-16
申请人： Kazuhiko KAJIGAYA , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko KAJIGAYA , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24 , G11C8/08 , H01L27/108
CPC分类号： G11C7/02 , G11C11/4074 , G11C11/4099 , H01L27/0207 , H01L27/0688 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/91
摘要： A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise.
摘要翻译：半导体存储器件（例如DRAM）由包括多个存储单元，多个字线驱动器，多个读出放大器和多个虚拟电容器的存储单元阵列构成。每个存储单元包括晶体管和电容器，位于字线和位线之间的交点处。电容器的第一电极连接到存储单元中的晶体管。虚拟电容器的第一电极连接在一起并被提供第二电位（例如VDD或VSS）。虚拟电容器的第二电极与存储单元的电容器的第二电极连接在一起并被提供有第一电位（例如VPL）。虚拟电容器用作板电压VPL的平滑电容，以减少板噪声。

6. 发明授权

US08988958B2 Sense amplifier circuit and semiconductor device 有权
公开(公告)号：US08988958B2
公开(公告)日：2015-03-24
申请号：US14306293
申请日：2014-06-17
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Yasutoshi Yamada
IPC分类号： G11C7/00 , G11C7/06 , G11C11/4091 , G11C5/14 , G11C7/10
CPC分类号： G11C7/06 , G11C5/147 , G11C7/065 , G11C7/067 , G11C7/1087 , G11C11/4091
摘要： A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

7. 发明授权

US08605532B2 Semiconductor device having hierarchical bit line structure 有权
标题翻译：具有分层位线结构的半导体器件
公开(公告)号：US08605532B2
公开(公告)日：2013-12-10
申请号：US13299285
申请日：2011-11-17
申请人： Kazuhiko Kajigaya , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Yasutoshi Yamada
IPC分类号： G11C7/00 , G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C7/06 , G11C7/1048 , G11C8/12 , G11C11/402 , G11C11/406 , G11C11/4091 , G11C11/4097
摘要： Disclosed herein is a semiconductor device comprising a memory cell, a local bit line coupled to the memory cell, a global bit line provided correspondingly to the local bit line, and a bit line control circuit coupled between the local bit line and the global bit line. The bit line control circuit includes a restoring circuit that is activated in a refresh mode to refresh data of the memory cell while being in electrical isolation from the global bit line.
摘要翻译：本文公开了一种半导体器件，包括存储器单元，耦合到存储器单元的局部位线，对应于局部位线提供的全局位线，以及耦合在局部位线和全局位线之间的位线控制电路。位线控制电路包括在刷新模式下被激活以在与全局位线电隔离的同时刷新存储器单元的数据的恢复电路。

8. 发明授权

US08217541B2 Wiring component for motor coil 失效
标题翻译：电机线圈接线部件
公开(公告)号：US08217541B2
公开(公告)日：2012-07-10
申请号：US12609278
申请日：2009-10-30
申请人： Toshiya Sugiyama , Jun Abiko , Yasutoshi Yamada , Hiroyuki Nagata
发明人： Toshiya Sugiyama , Jun Abiko , Yasutoshi Yamada , Hiroyuki Nagata
IPC分类号： H02K11/00 , H02K3/00 , H02K3/46
CPC分类号： H02K3/50 , H02K2203/06 , H02K2203/09
摘要： A wiring component for a motor coil includes a wire coil configured by a plurality of wire segments arranged in a circumferential direction so as to form a ring shape, each of the wire segments including an arc-shaped main-body portion made of a conductive wire rod bent in an arc shape, protruding portions formed at both end portions of the main-body portion, and upright portions respectively formed at end portions of the protruding portions in a manner of bending one of end portions of each of the protruding portions so that the upright portions protrude in a direction vertical relative to a planar surface including the main-body portion. The wire coil is arranged to form a plurality of layers, thereby forming a cylindrical shape, and the upright portions, at which the adjacent wire segments contact each other in the circumferential direction thereof, are electrically connected to each other.
摘要翻译：一种电动机线圈用配线部件，具有由圆周方向配置的多个线段构成的线圈构成环状，每个线段包括由导线形成的圆弧状的主体部杆弯曲成弧形，形成在主体部分的两个端部的突出部分和分别形成在突出部分的端部处的竖立部分，以弯曲每个突出部分的一个端部的方式使得直立部分在相对于包括主体部分的平面的垂直方向上突出。线圈被布置成形成多个层，从而形成圆柱形，并且相邻的线段在其圆周方向上彼此接触的直立部分彼此电连接。

9. 发明申请

US20120127816A1 SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE 有权
标题翻译：具有分层线结构的半导体器件
公开(公告)号：US20120127816A1
公开(公告)日：2012-05-24
申请号：US13299285
申请日：2011-11-17
申请人： Kazuhiko Kajigaya , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Yasutoshi Yamada
IPC分类号： G11C7/06 , G11C11/402
CPC分类号： G11C7/06 , G11C7/1048 , G11C8/12 , G11C11/402 , G11C11/406 , G11C11/4091 , G11C11/4097
摘要： Disclosed herein is a semiconductor device comprising a memory cell, a local bit line coupled to the memory cell, a global bit line provided correspondingly to the local bit line, and a bit line control circuit coupled between the local bit line and the global bit line. The bit line control circuit includes a restoring circuit that is activated in a refresh mode to refresh data of the memory cell while being in electrical isolation from the global bit line.
摘要翻译：本文公开了一种半导体器件，包括存储器单元，耦合到存储器单元的局部位线，对应于局部位线提供的全局位线，以及耦合在局部位线和全局位线之间的位线控制电路。位线控制电路包括在刷新模式下被激活以在与全局位线电隔离的同时刷新存储器单元的数据的恢复电路。

10. 发明申请

US20110220968A1 DEVICE 有权
标题翻译：设备
公开(公告)号：US20110220968A1
公开(公告)日：2011-09-15
申请号：US13042108
申请日：2011-03-07
申请人： Shinichi TAKAYAMA , Yasutoshi YAMADA
发明人： Shinichi TAKAYAMA , Yasutoshi YAMADA
IPC分类号： H01L23/528
CPC分类号： H01L27/0207 , G11C11/4094 , G11C11/4096 , G11C11/4097 , H01L27/10811 , H01L27/10876 , H01L27/10885 , H01L27/10897
摘要： A device includes a semiconductor substrate, a first local bit line formed in the semiconductor substrate and elongated in a first direction, a first insulating layer on the semiconductor substrate, a first global bit line formed on the first insulating layer, a first path formed in the first insulating layer to couple a first end of the first local bit line with the first global bit line, and a second path formed in the first insulating layer to couple a second end of the first local bit line with the first global bit line.
摘要翻译：一种器件包括半导体衬底，形成在半导体衬底中并在第一方向上延伸的第一局部位线，在半导体衬底上的第一绝缘层，形成在第一绝缘层上的第一全局位线，形成在第一绝缘层上的第一通路所述第一绝缘层将所述第一局部位线的第一端与所述第一全局位线耦合，以及形成在所述第一绝缘层中以将所述第一局部位线的第二端与所述第一全局位线耦合的第二路径。

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