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1. 发明授权

US07933141B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07933141B2
公开(公告)日：2011-04-26
申请号：US12416432
申请日：2009-04-01
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24
CPC分类号： G11C5/147 , G11C7/04 , G11C11/4076 , G11C11/4091 , G11C11/4097
摘要： In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.
摘要翻译：在半导体存储器件中，存储单元通过局部位线和全局位线与本地读出放大器和全局读出放大器连接。本地读出放大器是包括单个MOS晶体管的单端读出放大器，其检测当与存储单元读取和写入数据时变化的局部位线的电位。监视MOS晶体管的阈值电压，以产生高电平写入电压和低电平写入电压，这些电压根据监视结果进行校正和移位，从而通过以下方式适当地执行对存储器单元的重新加载操作：全局局部感测放大器。因此，可以消除阈值电压的温度变化和由于制造工艺的分散造成的阈值电压的偏移。

2. 发明授权

US07903449B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07903449B2
公开(公告)日：2011-03-08
申请号：US12485568
申请日：2009-06-16
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24
CPC分类号： G11C7/02 , G11C11/4074 , G11C11/4099 , H01L27/0207 , H01L27/0688 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/91
摘要： A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise.
摘要翻译：半导体存储器件（例如DRAM）由包括多个存储单元，多个字线驱动器，多个读出放大器和多个虚拟电容器的存储单元阵列构成。每个存储单元包括晶体管和电容器，位于字线和位线之间的交点处。电容器的第一电极连接到存储单元中的晶体管。虚拟电容器的第一电极连接在一起并被提供第二电位（例如VDD或VSS）。虚拟电容器的第二电极与存储单元的电容器的第二电极连接在一起并被提供有第一电位（例如VPL）。虚拟电容器用作板电压VPL的平滑电容，以减少板噪声。

3. 发明申请

US20090251948A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090251948A1
公开(公告)日：2009-10-08
申请号：US12416432
申请日：2009-04-01
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24 , G11C7/06 , G11C7/00
CPC分类号： G11C5/147 , G11C7/04 , G11C11/4076 , G11C11/4091 , G11C11/4097
摘要： In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.
摘要翻译：在半导体存储器件中，存储单元通过局部位线和全局位线与本地读出放大器和全局读出放大器连接。本地读出放大器是包括单个MOS晶体管的单端读出放大器，其检测当与存储单元读取和写入数据时变化的局部位线的电位。监视MOS晶体管的阈值电压，以产生高电平写入电压和低电平写入电压，这些电压根据监视结果进行校正和移位，从而通过对存储器单元适当地执行重新加载操作全局局部感测放大器。因此，可以消除阈值电压的温度变化和由于制造工艺的分散造成的阈值电压的偏移。

4. 发明授权

US07804700B2 Semiconductor memory device with reduced coupling noise 有权
标题翻译：具有降低耦合噪声的半导体存储器件
公开(公告)号：US07804700B2
公开(公告)日：2010-09-28
申请号：US12343086
申请日：2008-12-23
申请人： Yasutoshi Yamada , Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Yasutoshi Yamada , Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C5/06 , G11C11/34 , G11C7/00
CPC分类号： G11C7/02 , G11C7/12 , G11C7/18 , G11C8/04 , G11C8/08 , G11C8/12 , G11C11/4094 , G11C11/4097
摘要： A semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at the intersections of the plurality of word lines and the plurality of bit lines and each of that includes a MIS transistor and a memory element, a decoder circuit for selecting a plurality of word lines, and a sense-amplifier circuit for determining information that is read from any of the plurality of memory cells to any of the plurality of bit lines, wherein a twist connector for switching the wiring order of the plurality of word lines is provided and level-stabilizing circuits, for supplying the potential level of a non-selected state to the plurality of word lines in the non-selected state are arranged in the area below the twist connector.
摘要翻译：半导体器件包括多个字线，多个位线，设置在多个字线和多个位线的交点处的多个存储单元，其中每一个包括MIS晶体管和存储元件，用于选择多个字线的解码器电路，以及用于确定从多个存储单元中的任何一个读取到多个位线中的任一个的信息的读出放大器电路，其中，用于切换多个字线的布线顺序的扭转连接器提供多个字线，并且用于将未选择状态的电位电平提供给未选择状态的多个字线的电平稳定电路被布置在扭转连接器下方的区域中。

5. 发明申请

US20090175064A1 SEMICONDUCTOR MEMORY DEVICE WITH REDUCED COUPLING NOISE 有权
标题翻译：具有减少耦合噪声的半导体存储器件
公开(公告)号：US20090175064A1
公开(公告)日：2009-07-09
申请号：US12343086
申请日：2008-12-23
申请人： Yasutoshi Yamada , Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Yasutoshi Yamada , Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C5/06 , G11C11/34 , G11C7/00
CPC分类号： G11C7/02 , G11C7/12 , G11C7/18 , G11C8/04 , G11C8/08 , G11C8/12 , G11C11/4094 , G11C11/4097
摘要： A semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at the intersections of the plurality of word lines and the plurality of bit lines and each of that includes a MIS transistor and a memory element, a decoder circuit for selecting a plurality of word lines, and a sense-amplifier circuit for determining information that is read from any of the plurality of memory cells to any of the plurality of bit lines, wherein a twist connector for switching the wiring order of the plurality of word lines is provided and level-stabilizing circuits, for supplying the potential level of a non-selected state to the plurality of word lines in the non-selected state are arranged in the area below the twist connector.
摘要翻译：半导体器件包括多个字线，多个位线，设置在多个字线和多个位线的交点处的多个存储单元，其中每一个包括一个MIS晶体管和一个存储元件，用于选择多个字线的解码器电路，以及用于确定从多个存储单元中的任何一个读取到多个位线中的任一个的信息的读出放大器电路，其中，用于切换多个字线的布线顺序的扭转连接器提供多个字线，并且用于将未选择状态的电位电平提供给未选择状态的多个字线的电平稳定电路被布置在扭转连接器下方的区域中。

6. 发明授权

US07505299B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07505299B2
公开(公告)日：2009-03-17
申请号：US11976531
申请日：2007-10-25
申请人： Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Tomonori Sekiguchi , Kazuhiko Kajigaya
发明人： Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Tomonori Sekiguchi , Kazuhiko Kajigaya
IPC分类号： G11C5/06 , G11C11/24 , G11C7/02 , G11C8/00
CPC分类号： G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10814 , H01L27/10873
摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.
摘要翻译：提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。当访问存储器单元时，两个晶体管被激活并且读取该信息。当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。

7. 发明申请

US20060158924A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060158924A1
公开(公告)日：2006-07-20
申请号：US11280170
申请日：2005-11-17
申请人： Tomonori Sekiguchi , Satoru Akiyama , Riichiro Takemura , Satoru Hanzawa , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Satoru Akiyama , Riichiro Takemura , Satoru Hanzawa , Kazuhiko Kajigaya
IPC分类号： G11C11/24
CPC分类号： G11C11/4094 , G11C7/12 , G11C7/18 , G11C11/4074 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10882
摘要： A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.
摘要翻译：从外部输入写命令，位线的电压变为VDL和VSS，以及根据存储单元的阈值电压（LVT：低阈值电压，MVT：中间阈值电压，HVT：高阈值电压）的电压晶体管经由存储单元晶体管写入电容器的存储节点。此后，当连接到电容器的板侧的板线从电压VPL驱动到电压VPH并且存储节点的电压由于耦合而增加时，位线的电压VDL被降低到电压VDP，并且根据存储单元晶体管的阈值电压的电平降低过度写入存储节点的电压，从而减小由于阈值电压的变化引起的存储节点的电压的变化。

8. 发明申请

US20050056876A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050056876A1
公开(公告)日：2005-03-17
申请号：US10975494
申请日：2004-10-29
申请人： Shinichi Miyatake , Kazuhiko Kajigaya , Kazuyuki Miyazawa , Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata
发明人： Shinichi Miyatake , Kazuhiko Kajigaya , Kazuyuki Miyazawa , Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata
IPC分类号： G11C11/401 , G11C7/18 , G11C11/403 , G11C11/405 , G11C11/406 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/0328 , H01L31/119
CPC分类号： H01L27/108 , G11C7/18 , G11C11/403 , G11C11/406 , G11C11/40615 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10814 , H01L27/10885 , H01L27/10897 , Y10S257/905 , Y10S257/906
摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6 F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2 F and smaller than 4 F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.
摘要翻译：提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期，实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低，高速读出时间，确保自刷新时间长的刷新周期。采用单交点单元两个单元/位方法的DRAM具有采用单交叉6 F 2单元的双单元结构，其结构是：存储单元布置在对应于a 位线对和字线; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。另外，硅衬底中的有源区域形成每个存储单元的晶体管的源极，沟道和漏极，相对于位线对的方向倾斜地形成。

9. 发明授权

US06538912B2 Semiconductor device 有权
公开(公告)号：US06538912B2
公开(公告)日：2003-03-25
申请号：US10139330
申请日：2002-05-07
申请人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
发明人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
IPC分类号： G11C1100
CPC分类号： H01L27/10894 , G11C11/4097 , H01L27/10897
摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.

10. 发明授权

US06400596B2 Semiconductor memory device using open data line arrangement 有权
标题翻译：半导体存储器件采用开放数据线布置
公开(公告)号：US06400596B2
公开(公告)日：2002-06-04
申请号：US09725107
申请日：2000-11-29
申请人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
发明人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
IPC分类号： G11C1100
CPC分类号： H01L27/10894 , G11C11/4097 , H01L27/10897
摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.
摘要翻译：当使用相移方法作为光刻技术时，将读出放大器交替放置在能够实现DRAM面积减小的一个交叉点存储器中，难以在读出放大器与每个读出放大器之间的边界区域中布置数据线内存阵列因此，提供了根据本发明的半导体器件。在半导体器件中，在副存储器阵列内或插入其间的两条数据线被连接到相邻的读出放大器，作为用于当读出放大器交替地从子存储器阵列（SMA）到读出放大器（SA）的数据线绘制的系统放置即，分别连接到两个相邻读出放大器的数据线之间的数据线的数目被设置为偶数（0,2,4 ...）。由于上述结构，可以避免在读出放大器块和子存储器阵列连接的部分中的断路和短路，并且便于连接布局。

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