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1. 发明授权

US06975131B2 Integrated module having a delay element 失效
标题翻译：具有延迟元件的集成模块
公开(公告)号：US06975131B2
公开(公告)日：2005-12-13
申请号：US10783377
申请日：2004-02-20
申请人： Kazimierz Szczypinski , Johann Pfeiffer
发明人： Kazimierz Szczypinski , Johann Pfeiffer
IPC分类号： G01R31/30 , H01L23/544 , H03K5/159 , G01R31/26
CPC分类号： G01R31/3016 , H01L22/34 , H01L2924/0002 , H03K5/159 , H01L2924/00
摘要： Integrated module having a circuit and a plurality of input/output terminals, each of the input/output terminals being connected to a driver circuit for driving output signals and to a reception circuit for receiving input signals, a first delay element with a first delay time being provided in the integrated module, which delay element can be connected into a signal path of a circuit-internal signal or can be disconnected, in order to delay or to accelerate the circuit-internal signal, wherein provision is made of a first test delay element at a first input/output terminal pair which is embodied in a manner structurally identical to the first delay element, in order, in a test operation, to determine the delay time by means of the signal propagation time between the two input/output terminals of the first input/output terminal pair.
摘要翻译：具有电路和多个输入/输出端子的集成模块，每个输入/输出端子连接到用于驱动输出信号的驱动电路和用于接收输入信号的接收电路，具有第一延迟时间的第一延迟元件提供在集成模块中，该延迟元件可以连接到电路内部信号的信号路径中或者可以被断开，以便延迟或加速电路内部信号，其中提供第一测试延迟在第一输入/输出端子对上的元件以与第一延迟元件结构相同的方式体现，按照测试操作，通过两个输入/输出端子之间的信号传播时间来确定延迟时间的第一输入/输出端子对。

2. 发明授权

US06917562B2 Semi-conductor component with clock relaying device 失效
标题翻译：带有时钟中继装置的半导体元件
公开(公告)号：US06917562B2
公开(公告)日：2005-07-12
申请号：US10658741
申请日：2003-09-10
申请人： Andre Schaefer , Johann Pfeiffer , Kazimierz Szczypinski
发明人： Andre Schaefer , Johann Pfeiffer , Kazimierz Szczypinski
IPC分类号： G11C7/22 , G11C11/4076 , G11C7/00
CPC分类号： G11C29/12015 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： The invention involves a component with a connection (3b), as well as at least one further connection (3a), whereby differential input clock pulses (CLK, CLKT; /CLK, /CLKT) can be applied to the connections (3a, 3b), or a single input clock pulse (CLK, CLKT) applied to the connection (3b) and/or to the further connection (3a)—, and where the component in addition has a first and a second pulse relay device (50, 51), where the first pulse relay device (50) has been provided for relaying differential input clock pulses (CLK, CLKT; /CLK, /CLKT), and the second pulse relay device (51) for relaying a single input clock pulse (CLK, CLKT).
摘要翻译：本发明涉及具有连接（3b）的组件以及至少一个另外的连接（3a），由此差分输入时钟脉冲（CLK，CLK，T CLK，/ CLK，可以应用于连接（3a，3b）或施加到连接（3b）上的单个输入时钟脉冲（CLK，CLK＆lt; T＆gt;）和或另外的连接（3a） - ，并且其中所述组件另外具有第一和第二脉冲中继设备（50,51），其中所述第一脉冲中继设备（50）已被提供用于中继差分输入时钟用于中继单个输入时钟脉冲（CLK，CLK T ）。

3. 发明授权

US06738309B2 Semiconductor memory and method for operating the semiconductor memory 失效
标题翻译：半导体存储器和半导体存储器的操作方法
公开(公告)号：US06738309B2
公开(公告)日：2004-05-18
申请号：US10154597
申请日：2002-05-23
申请人： Alexander Benedix , Kazimierz Szczypinski , Helmut Fischer , Johann Pfeiffer
发明人： Alexander Benedix , Kazimierz Szczypinski , Helmut Fischer , Johann Pfeiffer
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/22 , G11C7/222
摘要： A semiconductor memory is described which has a clock input, a signal input, a data output, a measuring device, a control circuit, and a latency. The latency elapses between the activation of the signal input and the availability of the data to be read at the data output. A clock signal is fed to the clock input. On the basis of the clock signal, the measuring device determines a value for the latency and the control circuit configures the semiconductor memory with the determined value for the operation of the semiconductor memory.
摘要翻译：描述了具有时钟输入，信号输入，数据输出，测量装置，控制电路和等待时间的半导体存储器。在信号输入的激活和在数据输出端要读取的数据的可用性之间经过了延迟。时钟信号被馈送到时钟输入。基于时钟信号，测量装置确定延迟的值，并且控制电路以半导体存储器的操作的确定值配置半导体存储器。

4. 发明申请

US20060018165A1 Digital RAM memory circuit with an expanded command structure 失效
标题翻译：具有扩展命令结构的数字RAM存储器电路
公开(公告)号：US20060018165A1
公开(公告)日：2006-01-26
申请号：US11178915
申请日：2005-07-11
申请人： Kazimierz Szczypinski
发明人： Kazimierz Szczypinski
IPC分类号： G11C7/10
CPC分类号： G11C11/4076 , G11C7/1078 , G11C7/109
摘要： The subject matter of the invention is a digital memory circuit having a multiplicity of memory cells, address terminals for applying address information for addressing respectively selected memory cells, data terminals for inputting and outputting the memory data which is to be written into, or has been read out at the addressed memory cells, an internal control device which responds to control commands as a function of external command code words in order to initiate operations of the memory circuit, and a plurality of parallel command terminals for receiving external multibit command code words, in each case in parallel format. According to the invention, at least one serial command terminal with a downstream serial command decoder is additionally provided for receiving and decoding external command code words, in each case as a serial bit sequence. The subject matter of the invention is also a memory controller which is designed to communicate with a memory circuit according to the invention and for this purpose has both a multiplicity of parallel command outputs and at least one serial command output for transmitting command code words to the memory circuit, in each case as a serial bit sequence.
摘要翻译：本发明的主题是具有多个存储器单元的数字存储器电路，用于施加用于寻址分别选择的存储单元的地址信息的地址端子，用于输入和输出要写入或已经被存储的存储器数据的数据端子在所寻址的存储器单元中读出，内部控制装置，其响应于作为外部命令代码字的函数的控制命令，以便启动存储器电路的操作;以及多个并行命令终端，用于接收外部多位命令代码字，在每种情况下都是并行格式。根据本发明，另外提供至少一个具有下游串行命令解码器的串行命令终端，用于接收和解码外部命令码字，在每种情况下都作为串行比特序列。本发明的主题还是一种存储器控制器，其被设计为与根据本发明的存储器电路通信，并且为此目的具有多个并行命令输出和至少一个串行命令输出，用于将命令代码字发送到存储器电路，在每种情况下都作为串行位序列。

5. 发明授权

US06771527B2 Integrated DRAM memory component 失效
标题翻译：集成DRAM存储器组件
公开(公告)号：US06771527B2
公开(公告)日：2004-08-03
申请号：US10650818
申请日：2003-08-28
申请人： Helmut Fischer , Athanasia Chrysostomides , Kazimierz Szczypinski
发明人： Helmut Fischer , Athanasia Chrysostomides , Kazimierz Szczypinski
IPC分类号： G11C506
CPC分类号： G11C11/4097 , H01L27/10897
摘要： An integrated DRAM memory component has sense amplifiers which, respectively within the framework of the integrated component, are formed from a multiplicity of transistor structures, arranged regularly in cell arrays, and signal interconnect structures with amplification transistors for bit line signal amplification. The amplification transistors are of identical design and they lie opposite one another in pairs in adjacent transistor rows. Signal interconnects, which are associated with the transistor rows and run parallel thereto, supply actuation signals. The signal interconnects for the actuation signals have the same arrangement symmetry as the amplification transistors, which means that the amplification transistors in adjacent transistor rows are in the same signal interconnect proximity.
摘要翻译：集成DRAM存储器组件具有读出放大器，其分别在集成部件的框架内由从单元阵列规则排列的多个晶体管结构以及具有用于位线信号放大的放大晶体管的信号互连结构形成。放大晶体管具有相同的设计，并且它们在相邻的晶体管行中成对地相对置。与晶体管行相关联并与其并行延伸的信号互连提供致动信号。用于致动信号的信号互连具有与放大晶体管相同的布置对称性，这意味着相邻晶体管行中的放大晶体管处于相同的信号互连接近。

6. 发明授权

US09153297B2 Integrated circuit and method for manufacturing the same 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US09153297B2
公开(公告)日：2015-10-06
申请号：US12061812
申请日：2008-04-03
申请人： Kazimierz Szczypinski , Wen-Ming Lee
发明人： Kazimierz Szczypinski , Wen-Ming Lee
IPC分类号： H03K3/00 , G11C7/10 , G11C11/4093
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C11/4093
摘要： An integrated circuit comprising at least one signal path which is adapted to route at least one signal from an origin to a target block, said signal path comprising at least an adjustable driver circuit comprising an input and an output, which is adapted to receive an electric signal having a first signal power as an input signal and which is adapted to provide an electric signal having a second signal power as an output signal is provided. Furthermore, the integrated circuit comprises at least one interconnect having an ohmic resistance and an electric capacity and being adapted to route said electric signal having a second signal power to said target block. Furthermore, a method for manufacturing such an integrated circuit is provided.
摘要翻译：一种集成电路，包括至少一个信号路径，其适于将至少一个信号从原点路由到目标块，所述信号路径至少包括可调节驱动器电路，其包括输入和输出，其适于接收电提供具有第一信号功率作为输入信号并且适于提供具有第二信号功率的电信号作为输出信号的信号。此外，集成电路包括具有欧姆电阻和电容的至少一个互连，并且适于将具有第二信号功率的所述电信号路由到所述目标块。此外，提供了一种用于制造这种集成电路的方法。

7. 发明授权

US07123523B2 Integrated circuit having an input circuit 有权
标题翻译：具有输入电路的集成电路
公开(公告)号：US07123523B2
公开(公告)日：2006-10-17
申请号：US10670662
申请日：2003-09-25
申请人： Andre Schäfer , Kazimierz Szczypinski , Jens Polney
发明人： Andre Schäfer , Kazimierz Szczypinski , Jens Polney
IPC分类号： G11C7/00
CPC分类号： H03K19/0016
摘要： An integrated circuit, in particular an integrated memory circuit, has an input circuit for the purpose of receiving a signal. The input circuit has an activation input for an activation signal in order to activate the input circuit, in a manner dependent on the activation signal, for the purpose of receiving signals.
摘要翻译：集成电路，特别是集成存储器电路，具有用于接收信号的输入电路。为了接收信号，输入电路具有用于激活信号的激活输入，以便以取决于激活信号的方式激活输入电路。

8. 发明授权

US06880055B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06880055B2
公开(公告)日：2005-04-12
申请号：US10260899
申请日：2002-09-30
申请人： Eckhard Brass , Kazimierz Szczypinski
发明人： Eckhard Brass , Kazimierz Szczypinski
IPC分类号： G11C7/10 , G06F12/00
CPC分类号： G11C7/1045
摘要： So that semiconductor memory devices can be used optimally with regard to different possible operating frequencies, according to the invention, a register area is formed in which frequency information with regard to a present operating frequency can be stored in coded form and be retrieved for a configuration and adaptation of the semiconductor memory device.
摘要翻译：因此，根据本发明，可以对于不同的可能的工作频率来最佳地使用半导体存储器件，形成寄存器区域，其中关于当前工作频率的频率信息可以被编码形式存储并被检索用于配置以及半导体存储器件的适配。

9. 发明申请

US20090119472A1 CONTROL CIRCUIT IN A MEMORY CHIP 失效
标题翻译：内存芯片中的控制电路
公开(公告)号：US20090119472A1
公开(公告)日：2009-05-07
申请号：US12262124
申请日：2008-10-30
申请人： Kazimierz Szczypinski
发明人： Kazimierz Szczypinski
IPC分类号： G06F12/00 , G06F1/08 , G06F1/04
CPC分类号： G11C7/1027 , G11C7/1066 , G11C7/1078 , G11C7/109 , G11C7/225
摘要： Embodiments of the invention relate to a control circuit comprising a clock signal connection for receiving a system clock signal, a write signal connection for receiving a write signal, and a write control circuit for executing write commands, wherein the write control circuit is designed to start executing a write command when a write signal is applied to the write signal connection during an edge of the system clock signal.
摘要翻译：本发明的实施例涉及包括用于接收系统时钟信号的时钟信号连接，用于接收写信号的写信号连接和用于执行写命令的写控制电路的控制电路，其中写控制电路被设计为开始当在系统时钟信号的边沿期间写入信号被施加到写入信号连接时执行写入命令。

10. 发明授权

US07304515B2 Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process 有权
标题翻译：用于同步时钟脉冲的器件，以及时钟脉冲同步过程
公开(公告)号：US07304515B2
公开(公告)日：2007-12-04
申请号：US11041878
申请日：2005-01-25
申请人： Martin Brox , Patrick Heyne , Alessandro Minzoni , Rajashekhar Rao , Kazimierz Szczypinski
发明人： Martin Brox , Patrick Heyne , Alessandro Minzoni , Rajashekhar Rao , Kazimierz Szczypinski
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , G06F1/10 , G11C7/22 , G11C7/222 , G11C11/4076 , H03K5/135 , H03K2005/00097 , H03L7/0812
摘要： The invention involves a clock pulse synchronization process as well as a device to be used in the synchronization of clock pulses, including a first delay apparatus with variably controllable delay period, in which a clock pulse or a signal derived from it, has a variably controllable delay period imposed on it and is then emitted as a delayed signal. In addition to the first delay apparatus with variably controllable delay period, a second delay apparatus with variably controllable delay period is provided.
摘要翻译：本发明涉及时钟脉冲同步过程以及用于同步时钟脉冲的装置，包括具有可变可控延迟周期的第一延迟装置，其中时钟脉冲或从其导出的信号具有可变的可控制延迟周期被施加，然后作为延迟信号发射。除了具有可变可控延迟周期的第一延迟装置之外，还提供了具有可变可控延迟周期的第二延迟装置。

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