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1. 发明授权

US07123523B2 Integrated circuit having an input circuit 有权
标题翻译：具有输入电路的集成电路
公开(公告)号：US07123523B2
公开(公告)日：2006-10-17
申请号：US10670662
申请日：2003-09-25
申请人： Andre Schäfer , Kazimierz Szczypinski , Jens Polney
发明人： Andre Schäfer , Kazimierz Szczypinski , Jens Polney
IPC分类号： G11C7/00
CPC分类号： H03K19/0016
摘要： An integrated circuit, in particular an integrated memory circuit, has an input circuit for the purpose of receiving a signal. The input circuit has an activation input for an activation signal in order to activate the input circuit, in a manner dependent on the activation signal, for the purpose of receiving signals.
摘要翻译：集成电路，特别是集成存储器电路，具有用于接收信号的输入电路。为了接收信号，输入电路具有用于激活信号的激活输入，以便以取决于激活信号的方式激活输入电路。

2. 发明授权

US06363017B1 Method and apparatus for alternate operation of a random access memory in single-memory operating mode and in combined multi-memory operating mode 有权
公开(公告)号：US06363017B1
公开(公告)日：2002-03-26
申请号：US09766465
申请日：2001-01-19
申请人： Jens Polney
发明人： Jens Polney
IPC分类号： G11C700
摘要： In a random access memory, a sequence of selection signals for a combined multi-memory operating functionality is supplied on control lines which connect the control logic to each memory cell in a cell field when the memory is in a combined multi-memory operating mode, and a sequence of selection signals for the write enable functionality is supplied when the memory is in the single-memory operating mode.

3. 发明授权

US07573760B2 Integrated circuit for sampling a sequence of data packets at a data output 失效
标题翻译：用于在数据输出端采样数据包序列的集成电路
公开(公告)号：US07573760B2
公开(公告)日：2009-08-11
申请号：US11854463
申请日：2007-09-12
申请人： Christian Sichert , Rainer Bartenschlager , Franz Freimuth , Jens Polney
发明人： Christian Sichert , Rainer Bartenschlager , Franz Freimuth , Jens Polney
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069
摘要： An integrated circuit comprises a sampling circuit arranged at a data output of an operating section and operated by sampling edges, data packets appearing at the data output in response to a sequence of request commands, and a control section configured to produce the sampling edges, the control section comprising at least two transmission branches each comprising a copy of the operating section. Pulse trains are applied to the transmission branches which have the same waveform as the sequence of request commands and are delayed relative to one another, wherein the first pulse train is contemporaneous with the sequence of request commands. The sampling edges are produced from leading edges of the pulse trains which appear at the outputs of the transmission branches.
摘要翻译：集成电路包括布置在操作部分的数据输出端并通过采样边缘进行操作的采样电路，响应于请求命令序列出现在数据输出处的数据分组，以及被配置为产生采样边缘的控制部分，控制部分包括至少两个传输分支，每个传输分支包括操作部分的副本。脉冲串被施加到具有与请求命令序列相同的波形的传输分支，并相对于彼此延迟，其中第一脉冲串与请求命令的顺序同时存在。采样边缘由出现在传输分支输出端的脉冲串的前沿产生。

4. 发明授权

US07554875B2 Bus structure, memory chip and integrated circuit 失效
标题翻译：总线结构，存储芯片和集成电路
公开(公告)号：US07554875B2
公开(公告)日：2009-06-30
申请号：US11700399
申请日：2007-01-31
申请人： Christian Sichert , Rainer Bartenschlager , Jens Polney
发明人： Christian Sichert , Rainer Bartenschlager , Jens Polney
IPC分类号： G11C8/00
CPC分类号： G06F13/4243 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096
摘要： A bus structure comprises a plurality of driver circuits, each driver circuit comprising an input for a first signal and a terminal for an output signal wherein each driver circuit is capable of providing the output signal at the terminal upon receipt of the first signal, a parallel bus comprising a plurality of output signal lines at a receiving end, being connectable to a target component, each of the signal lines extending at least from the receiving end to the terminal of a different one of the plurality of driver circuits, such that a length of the output signal line between the receiving end and the respective driver circuits decreases in a connection order among the plurality of driver circuits, and a signal line coupled to each of the inputs of the driver circuits in the connection order.
摘要翻译：总线结构包括多个驱动器电路，每个驱动电路包括用于第一信号的输入端和用于输出信号的端子，其中每个驱动电路能够在接收到第一信号时在端子处提供输出信号，并联总线包括在接收端处的多个输出信号线，可连接到目标分量，每个信号线至少从多个驱动器电路中的不同驱动电路的接收端延伸到终端，使得长度接收端与各个驱动电路之间的输出信号线在多个驱动电路之间以连接顺序减小，以及以连接顺序耦合到驱动器电路的每个输入的信号线。

5. 发明申请

US20080061852A1 INTEGRATED CIRCUIT FOR SAMPLING A SEQUENCE OF DATA PACKETS AT A DATA OUTPUT 失效
标题翻译：用于在数据输出中采集数据包序列的集成电路
公开(公告)号：US20080061852A1
公开(公告)日：2008-03-13
申请号：US11854463
申请日：2007-09-12
申请人： Christian Sichert , Rainer Bartenschlager , Franz Freimuth , Jens Polney
发明人： Christian Sichert , Rainer Bartenschlager , Franz Freimuth , Jens Polney
IPC分类号： H03L7/00
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069
摘要： An integrated circuit comprises a sampling circuit arranged at a data output of an operating section and operated by sampling edges, data packets appearing at the data output in response to a sequence of request commands, and a control section configured to produce the sampling edges, the control section comprising at least two transmission branches each comprising a copy of the operating section. Pulse trains are applied to the transmission branches which have the same waveform as the sequence of request commands and are delayed relative to one another, wherein the first pulse train is contemporaneous with the sequence of request commands. The sampling edges are produced from leading edges of the pulse trains which appear at the outputs of the transmission branches.
摘要翻译：集成电路包括布置在操作部分的数据输出端并通过采样边缘进行操作的采样电路，响应于请求命令序列出现在数据输出处的数据分组，以及被配置为产生采样边缘的控制部分，控制部分包括至少两个传输分支，每个传输分支包括操作部分的副本。脉冲串被施加到具有与请求命令序列相同的波形的传输分支，并相对于彼此延迟，其中第一脉冲串与请求命令的顺序同时存在。采样边缘由出现在传输分支输出端的脉冲串的前沿产生。

6. 发明申请

US20060133172A1 Apparatus and method for writing to and/or reading from a memory cell in a semiconductor memory 审中-公开
标题翻译：用于向半导体存储器中的存储单元进行写入和/或读取的装置和方法
公开(公告)号：US20060133172A1
公开(公告)日：2006-06-22
申请号：US11283493
申请日：2005-11-18
申请人： Florian Schnabel , Jens Polney
发明人： Florian Schnabel , Jens Polney
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C5/146 , G11C11/4074 , G11C11/409
摘要： The invention proposes an apparatus for writing to and/or reading from a memory cell in a semiconductor memory having a selection transistor and a storage capacitor, where the apparatus has a device which is used to influence a threshold voltage for the selection transistor contrary to the influence of an ambient temperature. The invention also proposes a method for writing to and/or reading from a memory cell in a semiconductor memory having a selection transistor and a storage capacitor, where the method comprises the following method steps: a) an ambient temperature for the memory cell is ascertained, and b) an electrical voltage is applied to a substrate well in the selection transistor as a function of the ascertained ambient temperature such that a threshold voltage for the selection transistor is influenced contrary to the influence of an ambient temperature.
摘要翻译：本发明提出了一种用于在具有选择晶体管和存储电容器的半导体存储器中从存储单元写入和/或读取的装置，其中该装置具有用于影响与该选择晶体管相反的选择晶体管的阈值电压的装置环境温度的影响。本发明还提出了一种用于在具有选择晶体管和存储电容器的半导体存储器中的存储单元的写入和/或读取方法，其中该方法包括以下方法步骤：a）确定存储单元的环境温度并且b）作为所确定的环境温度的函数，在选择晶体管中的基板上施加电压，使得选择晶体管的阈值电压与环境温度的影响相反。

7. 发明申请

US20080181044A1 Bus structure, memory chip and integrated circuit 失效
标题翻译：总线结构，存储芯片和集成电路
公开(公告)号：US20080181044A1
公开(公告)日：2008-07-31
申请号：US11700399
申请日：2007-01-31
申请人： Christian Sichert , Rainer Bartenschlager , Jens Polney
发明人： Christian Sichert , Rainer Bartenschlager , Jens Polney
IPC分类号： H03K3/00 , G11C8/00
CPC分类号： G06F13/4243 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096
摘要： A bus structure comprises a plurality of driver circuits, each driver circuit comprising an input for a first signal and a terminal for an output signal wherein each driver circuit is capable of providing the output signal at the terminal upon receipt of the first signal, a parallel bus comprising a plurality of output signal lines at a receiving end, being connectable to a target component, each of the signal lines extending at least from the receiving end to the terminal of a different one of the plurality of driver circuits, such that a length of the output signal line between the receiving end and the respective driver circuits decreases in a connection order among the plurality of driver circuits, and a signal line coupled to each of the inputs of the driver circuits in the connection order.
摘要翻译：总线结构包括多个驱动器电路，每个驱动电路包括用于第一信号的输入端和用于输出信号的端子，其中每个驱动电路能够在接收到第一信号时在端子处提供输出信号，并联总线包括在接收端处的多个输出信号线，可连接到目标分量，每个信号线至少从多个驱动器电路中的不同驱动电路的接收端延伸到终端，使得长度接收端与各个驱动电路之间的输出信号线在多个驱动电路之间以连接顺序减小，以及以连接顺序耦合到驱动器电路的每个输入的信号线。

8. 发明授权

US06977862B2 Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit 失效
公开(公告)号：US06977862B2
公开(公告)日：2005-12-20
申请号：US10920559
申请日：2004-08-18
申请人： Florian Schnabel , Jens Polney
发明人： Florian Schnabel , Jens Polney
IPC分类号： G11C8/00 , G11C8/10 , G11C29/00
CPC分类号： G11C29/84
摘要： Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit are provided. One embodiment provides a method for addressing memory areas in a memory circuit with successive addresses, with either a regular memory area or a redundant memory area being addressed depending on the address, with an inactive state of a deactivation signal being set when addressing the regular memory area, which inactive state allows the addressing of the regular memory area, with the addressing of the regular memory area being blocked on the basis of an active state of the deactivation signal when addressing the redundant memory area, wherein a change is made from the active state of the deactivation signal to the inactive state of the deactivation signal before the application of the next address for addressing one of the memory areas.

9. 发明申请

US20050117416A1 Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit 失效
标题翻译：用于寻址存储器电路中的常规存储器区域和冗余存储器区域的地址解码电路和方法
公开(公告)号：US20050117416A1
公开(公告)日：2005-06-02
申请号：US10920559
申请日：2004-08-18
申请人： Florian Schnabel , Jens Polney
发明人： Florian Schnabel , Jens Polney
IPC分类号： G11C8/00 , G11C8/10 , G11C29/00
CPC分类号： G11C29/84
摘要： Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit are provided. One embodiment provides a method for addressing memory areas in a memory circuit with successive addresses, with either a regular memory area or a redundant memory area being addressed depending on the address, with an inactive state of a deactivation signal being set when addressing the regular memory area, which inactive state allows the addressing of the regular memory area, with the addressing of the regular memory area being blocked on the basis of an active state of the deactivation signal when addressing the redundant memory area, wherein a change is made from the active state of the deactivation signal to the inactive state of the deactivation signal before the application of the next address for addressing one of the memory areas.
摘要翻译：提供了用于寻址存储器电路中的常规存储区域和冗余存储器区域的地址解码电路和方法。一个实施例提供了一种用于利用具有连续地址来寻址存储器电路中的存储器区域的方法，其中根据地址寻址常规存储器区域或冗余存储器区域，在寻址常规存储器时设置去激活信号的非活动状态区域，其中所述非活动状态允许寻址常规存储器区域，其中当寻址冗余存储器区域时，基于去激活信号的活动状态来阻止常规存储器区域的寻址，其中，从激活在施加用于寻址存储区域之一的下一个地址之前，去激活信号的状态到去激活信号的无效状态。

10. 发明授权

US06525597B2 Circuit configuration with internal supply voltage 有权
公开(公告)号：US06525597B2
公开(公告)日：2003-02-25
申请号：US10008114
申请日：2001-11-08
申请人： Jens Polney
发明人： Jens Polney
IPC分类号： G05F110
CPC分类号： G11C7/1051 , G11C5/147 , G11C7/20 , H03K17/223
摘要： In integrated circuits with internally generated supply voltages, during the run-up of the internal voltage generators, unintentionally high currents can arise through switching stages connected to the internal supply voltage. A control circuit provides for the initialization of the switching stages during power-up. The control circuit contains an inverter that, in signal terms, can be driven by a precharge signal and, on the supply voltage side, is connected to the internal supply voltage via respective transistors. During power-up, the transistors are switched off and then switched on. The precharge signal is forwarded to the switching stage via a further inverter.

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