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1. 发明申请

US20050179478A1 Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process 有权
标题翻译：用于同步时钟脉冲的器件，以及时钟脉冲同步过程
公开(公告)号：US20050179478A1
公开(公告)日：2005-08-18
申请号：US11041878
申请日：2005-01-25
申请人： Martin Brox , Patrick Heyne , Alessandro Minzoni , Rajashekhar Rao , Kazimierz Szczypinski
发明人： Martin Brox , Patrick Heyne , Alessandro Minzoni , Rajashekhar Rao , Kazimierz Szczypinski
IPC分类号： G06F1/10 , G11C7/22 , G11C11/4076 , H03K5/00 , H03K5/135 , H03L7/081 , H03L7/06
CPC分类号： H03L7/0805 , G06F1/10 , G11C7/22 , G11C7/222 , G11C11/4076 , H03K5/135 , H03K2005/00097 , H03L7/0812
摘要： The invention involves a clock pulse synchronization process as well as a device (1, 101) to be used in the synchronization of clock pulses (CLK), containing a first delay apparatus (2a) with variably controllable delay period (tvar), in which a clock pulse (CLK) or a signal derived from it, has a variably controllable delay period (tvar) imposed on it and is then emitted as a delayed signal (FBA), characterized in that in addition to the first delay apparatus (2a) with variably controllable delay period (tvar), a second delay apparatus (2b) with variably controllable delay period (tvar) is provided.
摘要翻译：本发明涉及一种时钟脉冲同步过程以及在时钟脉冲（CLK）的同步中使用的装置（1,101），其包含具有可变可控延迟周期（t）的第一延迟装置（2a）其中时钟脉冲（CLK）或从其导出的信号具有施加在其上的可变可控延迟时段（t 0 var），然后作为延迟信号发射（FBA），其特征在于，除了具有可变可控延迟周期（tOUT var）的第一延迟装置（2a）之外，具有可变可控延迟周期（t）的第二延迟装置（2b） _{var ）。}

2. 发明授权

US07304515B2 Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process 有权
标题翻译：用于同步时钟脉冲的器件，以及时钟脉冲同步过程
公开(公告)号：US07304515B2
公开(公告)日：2007-12-04
申请号：US11041878
申请日：2005-01-25
申请人： Martin Brox , Patrick Heyne , Alessandro Minzoni , Rajashekhar Rao , Kazimierz Szczypinski
发明人： Martin Brox , Patrick Heyne , Alessandro Minzoni , Rajashekhar Rao , Kazimierz Szczypinski
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , G06F1/10 , G11C7/22 , G11C7/222 , G11C11/4076 , H03K5/135 , H03K2005/00097 , H03L7/0812
摘要： The invention involves a clock pulse synchronization process as well as a device to be used in the synchronization of clock pulses, including a first delay apparatus with variably controllable delay period, in which a clock pulse or a signal derived from it, has a variably controllable delay period imposed on it and is then emitted as a delayed signal. In addition to the first delay apparatus with variably controllable delay period, a second delay apparatus with variably controllable delay period is provided.
摘要翻译：本发明涉及时钟脉冲同步过程以及用于同步时钟脉冲的装置，包括具有可变可控延迟周期的第一延迟装置，其中时钟脉冲或从其导出的信号具有可变的可控制延迟周期被施加，然后作为延迟信号发射。除了具有可变可控延迟周期的第一延迟装置之外，还提供了具有可变可控延迟周期的第二延迟装置。

3. 发明授权

US07482849B2 Clock signal synchronizing device, and clock signal synchronizing method 有权
标题翻译：时钟信号同步装置和时钟信号同步方法
公开(公告)号：US07482849B2
公开(公告)日：2009-01-27
申请号：US11211084
申请日：2005-08-25
申请人： Martin Brox , Alessandro Minzoni
发明人： Martin Brox , Alessandro Minzoni
IPC分类号： H03L7/06
CPC分类号： H03K5/135
摘要： The invention relates to a clock signal synchronizing method, and to a clock signal synchronizing device (101) to be used with the synchronization of clock signals (CLK, DQS), comprising: a delay means (102) with a variably controllable delay time (tvar), in which a clock signal (CLK) or a signal obtained therefrom is input, is loaded with the variably controllable delay time (tvar), and is output as delayed clock signal, a phase comparator (104) for comparing the phase of the clock signal (CLK) or of the signal obtained therefrom with the phase of the delayed clock signal or of a signal obtained therefrom (DCLK, FB), characterized in that additionally a means (401, 116) is provided for activating and/or deactivating said clock signal synchronizing device (101) as a function of control signals (RD) evaluated by an evaluating means (402).
摘要翻译：本发明涉及一种时钟信号同步方法以及与时钟信号（CLK，DQS）的同步一起使用的时钟信号同步装置（101），包括：具有可变可控延迟时间的延迟装置（102）输入时钟信号（CLK）或从其获得的信号的tvar）被加载可变可控延迟时间（tvar），并作为延迟时钟信号输出，相位比较器（104）用于比较时钟信号（CLK）或由其获得的延迟时钟信号的相位或由其获得的信号（DCLK，FB）获得的信号的信号，其特征在于，还提供了用于激活和/或执行的装置（401,116）作为由评估装置（402）评估的控制信号（RD）的函数，去激活所述时钟信号同步装置（101）。

4. 发明授权

US06996026B2 Devices for synchronizing clock signals 失效
标题翻译：用于同步时钟信号的设备
公开(公告)号：US06996026B2
公开(公告)日：2006-02-07
申请号：US10834383
申请日：2004-04-29
申请人： Martin Brox , Alessandro Minzoni
发明人： Martin Brox , Alessandro Minzoni
IPC分类号： G11C8/00
CPC分类号： G11C7/222 , G11C7/22 , G11C11/4076 , H03L7/0812 , H03L7/087
摘要： A clock signal synchronizing device includes a first delay unit with variable delay time connected to an input circuit with a first delay time which receives a first clock signal and outputs a second clock signal. A second delay unit has a fixed delay time portion corresponding to the first delay time, and an additional variable delay time portion. A first phase comparison unit has a first input connected to the output of the input circuit, and a second input connected to the output of the second delay unit. The output signal controls the delay time of the first delay unit. A copy of the input circuit has an input connected to the output of the first delay unit. A second phase comparison unit has an input connected to the output of the copy, and an output signal controls the variable delay time portion of the second delay unit.
摘要翻译：时钟信号同步装置包括具有连续到输入电路的可变延迟时间的第一延迟单元，其具有接收第一时钟信号并输出第二时钟信号的第一延迟时间。第二延迟单元具有对应于第一延迟时间的固定延迟时间部分和附加可变延迟时间部分。第一相位比较单元具有连接到输入电路的输出的第一输入和连接到第二延迟单元的输出的第二输入。输出信号控制第一延迟单元的延迟时间。输入电路的副本具有连接到第一延迟单元的输出的输入。第二相位比较单元具有连接到副本的输出的输入，并且输出信号控制第二延迟单元的可变延迟时间部分。

5. 发明申请

US20070182468A1 Clock signal synchronizing device, and clock signal synchronizing method 有权
标题翻译：时钟信号同步装置和时钟信号同步方法
公开(公告)号：US20070182468A1
公开(公告)日：2007-08-09
申请号：US11211084
申请日：2005-08-25
申请人： Martin Brox , Alessandro Minzoni
发明人： Martin Brox , Alessandro Minzoni
IPC分类号： H03L7/06
CPC分类号： H03K5/135
摘要： The invention relates to a clock signal synchronizing method, and to a clock signal synchronizing device (101) to be used with the synchronization of clock signals (CLK, DQS), comprising: a delay means (102) with a variably controllable delay time (tvar), in which a clock signal (CLK) or a signal obtained therefrom is input, is loaded with the variably controllable delay time (tvar), and is output as delayed clock signal, a phase comparator (104) for comparing the phase of the clock signal (CLK) or of the signal obtained therefrom with the phase of the delayed clock signal or of a signal obtained therefrom (DCLK, FB), characterized in that additionally a means (401, 116) is provided for activating and/or deactivating said clock signal synchronizing device (101) as a function of control signals (RD) evaluated by an evaluating means (402).
摘要翻译：本发明涉及一种时钟信号同步方法以及与时钟信号（CLK，DQS）的同步一起使用的时钟信号同步装置（101），包括：具有可变可控延迟时间的延迟装置（102）其中输入了时钟信号（CLK）或从其获得的信号）被加载了可变可控延迟时间（t> var ），并被输出作为延迟时钟信号，用于将时钟信号（CLK）的相位或由其获得的信号与延迟的时钟信号的相位或从其获得的信号（DCLK，FB）进行比较的相位比较器（104），其特征在于另外还提供了一种用于根据由评估装置（402）评估的控制信号（RD）来激活和/或去激活所述时钟信号同步装置（101）的装置（401,116）。

6. 发明授权

US06765421B2 Duty-cycle correction circuit 有权
标题翻译：占空比校正电路
公开(公告)号：US06765421B2
公开(公告)日：2004-07-20
申请号：US10393525
申请日：2003-03-20
申请人： Martin Brox , Alessandro Minzoni
发明人： Martin Brox , Alessandro Minzoni
IPC分类号： H03K3017
CPC分类号： G06F1/06 , H03K5/133 , H03K5/1565 , H03K2005/00039 , H03L7/07 , H03L7/0812
摘要： An apparatus for generating two signals having a predetermined spacing between mutually corresponding signal edges includes first and second delay devices for delaying a clock signal and a complementary clock signal in response to respective first and second control signals. A first control signal generator generates the first control signal on the basis of the clock signal and the delayed clock signal. A second control signal generator generates the second control signal on the basis of the delayed clock signal and the delayed complementary clock signal. The second control signal generator causes the delayed clock signal and the delayed complementary clock signal to have a steady-state condition in which mutually corresponding edges thereof are separated by a pre-determined spacing.
摘要翻译：用于产生具有相互相应的信号边缘之间的预定间隔的两个信号的装置包括用于响应于相应的第一和第二控制信号延迟时钟信号和互补时钟信号的第一和第二延迟装置。第一控制信号发生器基于时钟信号和延迟的时钟信号产生第一控制信号。第二控制信号发生器基于延迟的时钟信号和延迟的互补时钟信号产生第二控制信号。第二控制信号发生器使得延迟的时钟信号和延迟的互补时钟信号具有稳态状态，其中相互对应的边缘被分隔预定的间隔。

7. 发明授权

US08918597B2 Digital data inversion flag generator circuit 有权
标题翻译：数字反转标志发生器电路
公开(公告)号：US08918597B2
公开(公告)日：2014-12-23
申请号：US12201876
申请日：2008-08-29
申请人： Martin Brox , Ronny Schneider
发明人： Martin Brox , Ronny Schneider
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , H03M7/00 , H03M5/00 , H03K19/003 , H03K19/23 , G11C7/10 , G11C7/06 , G06F13/42
CPC分类号： G06F13/4239
摘要： An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number. The digital flag generator circuit includes a first digital stage including a first plurality of binary logic circuits. Each of the binary logic circuits is configured to receive a subset of the data word.
摘要翻译：集成电路包括存储器单元阵列和数字标志发生器电路，该数字标志发生器电路被配置为基于从存储器单元发送的数据字中包含的逻辑零比特数是否大于阈值来生成数据反转标志。数字标志发生器电路包括包括第一多个二进制逻辑电路的第一数字级。每个二进制逻辑电路被配置为接收数据字的子集。

8. 发明授权

US08055857B2 Write access and subsequent read access to a memory device 有权
标题翻译：对存储设备进行写访问和后续读访问
公开(公告)号：US08055857B2
公开(公告)日：2011-11-08
申请号：US11936663
申请日：2007-11-07
申请人： Martin Brox , Rex Kho
发明人： Martin Brox , Rex Kho
IPC分类号： G06F13/36
CPC分类号： G11C7/10 , G06F13/1673 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1093
摘要： A memory device has a first memory area and a second memory area. A method for operating the memory device includes a write access to the first memory area and a read access to the second memory area.
摘要翻译：存储器设备具有第一存储器区域和第二存储器区域。用于操作存储器件的方法包括对第一存储器区域的写访问和对第二存储器区域的读访问。

9. 发明授权

US07757132B2 Memory with an output register for test data and process for testing a memory and memory module 失效
标题翻译：具有用于测试数据的输出寄存器和用于测试存储器和存储器模块的过程的存储器
公开(公告)号：US07757132B2
公开(公告)日：2010-07-13
申请号：US11752907
申请日：2007-05-23
申请人： Wolfgang Spirkl , Martin Brox
发明人： Wolfgang Spirkl , Martin Brox
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C2029/0405 , G11C2029/3602
摘要： The invention relates to a memory with a memory array with memory cells, with an input/output circuit which is connected to the memory cells and which interchanges data with the memory cells, with an output register which is connected to the input/output circuit, with the output register being used to output data via a data output, having an input register which is connected to a data input and to the input/output circuit, with the data input and the input register being used to input data into the memory cells, with test data being written to the output register in a test mode. The invention furthermore relates to a process for testing a memory and to a memory module.
摘要翻译：本发明涉及具有存储器单元的存储器阵列的存储器，其中输入/输出电路连接到存储器单元并且与存储器单元交换数据，以及连接到输入/输出电路的输出寄存器，其中输出寄存器用于经由数据输出输出数据，具有连接到数据输入端和输入/输出电路的输入寄存器，数据输入端和输入寄存器用于将数据输入存储单元测试数据以测试模式写入输出寄存器。本发明还涉及一种用于测试存储器和存储器模块的过程。

10. 发明申请

US20090271678A1 INTERFACE VOLTAGE ADJUSTMENT BASED ON ERROR DETECTION 有权
标题翻译：基于错误检测的接口电压调整
公开(公告)号：US20090271678A1
公开(公告)日：2009-10-29
申请号：US12109826
申请日：2008-04-25
申请人： Andreas Schneider , Markus Balb , Thomas Hein , Christoph Bilger , Martin Brox , Peter Gregorius , Michael Richter
发明人： Andreas Schneider , Markus Balb , Thomas Hein , Christoph Bilger , Martin Brox , Peter Gregorius , Michael Richter
IPC分类号： H03M13/00 , G06F11/07
CPC分类号： G11C29/021 , G06F11/1004 , G11C7/1006 , G11C11/401 , G11C11/4074 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/028 , G11C2029/0411 , H03M13/03
摘要： A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection.
摘要翻译：调整接口电压的方法包括在存储器件和控制器之间传输数据，以及检测数据传输中是否发生错误。基于检测来调整存储器件和控制器中的至少一个的接口电压。

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