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1. 发明申请

US20060018165A1 Digital RAM memory circuit with an expanded command structure 失效
标题翻译：具有扩展命令结构的数字RAM存储器电路
公开(公告)号：US20060018165A1
公开(公告)日：2006-01-26
申请号：US11178915
申请日：2005-07-11
申请人： Kazimierz Szczypinski
发明人： Kazimierz Szczypinski
IPC分类号： G11C7/10
CPC分类号： G11C11/4076 , G11C7/1078 , G11C7/109
摘要： The subject matter of the invention is a digital memory circuit having a multiplicity of memory cells, address terminals for applying address information for addressing respectively selected memory cells, data terminals for inputting and outputting the memory data which is to be written into, or has been read out at the addressed memory cells, an internal control device which responds to control commands as a function of external command code words in order to initiate operations of the memory circuit, and a plurality of parallel command terminals for receiving external multibit command code words, in each case in parallel format. According to the invention, at least one serial command terminal with a downstream serial command decoder is additionally provided for receiving and decoding external command code words, in each case as a serial bit sequence. The subject matter of the invention is also a memory controller which is designed to communicate with a memory circuit according to the invention and for this purpose has both a multiplicity of parallel command outputs and at least one serial command output for transmitting command code words to the memory circuit, in each case as a serial bit sequence.
摘要翻译：本发明的主题是具有多个存储器单元的数字存储器电路，用于施加用于寻址分别选择的存储单元的地址信息的地址端子，用于输入和输出要写入或已经被存储的存储器数据的数据端子在所寻址的存储器单元中读出，内部控制装置，其响应于作为外部命令代码字的函数的控制命令，以便启动存储器电路的操作;以及多个并行命令终端，用于接收外部多位命令代码字，在每种情况下都是并行格式。根据本发明，另外提供至少一个具有下游串行命令解码器的串行命令终端，用于接收和解码外部命令码字，在每种情况下都作为串行比特序列。本发明的主题还是一种存储器控制器，其被设计为与根据本发明的存储器电路通信，并且为此目的具有多个并行命令输出和至少一个串行命令输出，用于将命令代码字发送到存储器电路，在每种情况下都作为串行位序列。

2. 发明授权

US06771527B2 Integrated DRAM memory component 失效
标题翻译：集成DRAM存储器组件
公开(公告)号：US06771527B2
公开(公告)日：2004-08-03
申请号：US10650818
申请日：2003-08-28
申请人： Helmut Fischer , Athanasia Chrysostomides , Kazimierz Szczypinski
发明人： Helmut Fischer , Athanasia Chrysostomides , Kazimierz Szczypinski
IPC分类号： G11C506
CPC分类号： G11C11/4097 , H01L27/10897
摘要： An integrated DRAM memory component has sense amplifiers which, respectively within the framework of the integrated component, are formed from a multiplicity of transistor structures, arranged regularly in cell arrays, and signal interconnect structures with amplification transistors for bit line signal amplification. The amplification transistors are of identical design and they lie opposite one another in pairs in adjacent transistor rows. Signal interconnects, which are associated with the transistor rows and run parallel thereto, supply actuation signals. The signal interconnects for the actuation signals have the same arrangement symmetry as the amplification transistors, which means that the amplification transistors in adjacent transistor rows are in the same signal interconnect proximity.
摘要翻译：集成DRAM存储器组件具有读出放大器，其分别在集成部件的框架内由从单元阵列规则排列的多个晶体管结构以及具有用于位线信号放大的放大晶体管的信号互连结构形成。放大晶体管具有相同的设计，并且它们在相邻的晶体管行中成对地相对置。与晶体管行相关联并与其并行延伸的信号互连提供致动信号。用于致动信号的信号互连具有与放大晶体管相同的布置对称性，这意味着相邻晶体管行中的放大晶体管处于相同的信号互连接近。

3. 发明授权

US09153297B2 Integrated circuit and method for manufacturing the same 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US09153297B2
公开(公告)日：2015-10-06
申请号：US12061812
申请日：2008-04-03
申请人： Kazimierz Szczypinski , Wen-Ming Lee
发明人： Kazimierz Szczypinski , Wen-Ming Lee
IPC分类号： H03K3/00 , G11C7/10 , G11C11/4093
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C11/4093
摘要： An integrated circuit comprising at least one signal path which is adapted to route at least one signal from an origin to a target block, said signal path comprising at least an adjustable driver circuit comprising an input and an output, which is adapted to receive an electric signal having a first signal power as an input signal and which is adapted to provide an electric signal having a second signal power as an output signal is provided. Furthermore, the integrated circuit comprises at least one interconnect having an ohmic resistance and an electric capacity and being adapted to route said electric signal having a second signal power to said target block. Furthermore, a method for manufacturing such an integrated circuit is provided.
摘要翻译：一种集成电路，包括至少一个信号路径，其适于将至少一个信号从原点路由到目标块，所述信号路径至少包括可调节驱动器电路，其包括输入和输出，其适于接收电提供具有第一信号功率作为输入信号并且适于提供具有第二信号功率的电信号作为输出信号的信号。此外，集成电路包括具有欧姆电阻和电容的至少一个互连，并且适于将具有第二信号功率的所述电信号路由到所述目标块。此外，提供了一种用于制造这种集成电路的方法。

4. 发明授权

US07123523B2 Integrated circuit having an input circuit 有权
标题翻译：具有输入电路的集成电路
公开(公告)号：US07123523B2
公开(公告)日：2006-10-17
申请号：US10670662
申请日：2003-09-25
申请人： Andre Schäfer , Kazimierz Szczypinski , Jens Polney
发明人： Andre Schäfer , Kazimierz Szczypinski , Jens Polney
IPC分类号： G11C7/00
CPC分类号： H03K19/0016
摘要： An integrated circuit, in particular an integrated memory circuit, has an input circuit for the purpose of receiving a signal. The input circuit has an activation input for an activation signal in order to activate the input circuit, in a manner dependent on the activation signal, for the purpose of receiving signals.
摘要翻译：集成电路，特别是集成存储器电路，具有用于接收信号的输入电路。为了接收信号，输入电路具有用于激活信号的激活输入，以便以取决于激活信号的方式激活输入电路。

5. 发明授权

US06975131B2 Integrated module having a delay element 失效
标题翻译：具有延迟元件的集成模块
公开(公告)号：US06975131B2
公开(公告)日：2005-12-13
申请号：US10783377
申请日：2004-02-20
申请人： Kazimierz Szczypinski , Johann Pfeiffer
发明人： Kazimierz Szczypinski , Johann Pfeiffer
IPC分类号： G01R31/30 , H01L23/544 , H03K5/159 , G01R31/26
CPC分类号： G01R31/3016 , H01L22/34 , H01L2924/0002 , H03K5/159 , H01L2924/00
摘要： Integrated module having a circuit and a plurality of input/output terminals, each of the input/output terminals being connected to a driver circuit for driving output signals and to a reception circuit for receiving input signals, a first delay element with a first delay time being provided in the integrated module, which delay element can be connected into a signal path of a circuit-internal signal or can be disconnected, in order to delay or to accelerate the circuit-internal signal, wherein provision is made of a first test delay element at a first input/output terminal pair which is embodied in a manner structurally identical to the first delay element, in order, in a test operation, to determine the delay time by means of the signal propagation time between the two input/output terminals of the first input/output terminal pair.
摘要翻译：具有电路和多个输入/输出端子的集成模块，每个输入/输出端子连接到用于驱动输出信号的驱动电路和用于接收输入信号的接收电路，具有第一延迟时间的第一延迟元件提供在集成模块中，该延迟元件可以连接到电路内部信号的信号路径中或者可以被断开，以便延迟或加速电路内部信号，其中提供第一测试延迟在第一输入/输出端子对上的元件以与第一延迟元件结构相同的方式体现，按照测试操作，通过两个输入/输出端子之间的信号传播时间来确定延迟时间的第一输入/输出端子对。

6. 发明授权

US06880055B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06880055B2
公开(公告)日：2005-04-12
申请号：US10260899
申请日：2002-09-30
申请人： Eckhard Brass , Kazimierz Szczypinski
发明人： Eckhard Brass , Kazimierz Szczypinski
IPC分类号： G11C7/10 , G06F12/00
CPC分类号： G11C7/1045
摘要： So that semiconductor memory devices can be used optimally with regard to different possible operating frequencies, according to the invention, a register area is formed in which frequency information with regard to a present operating frequency can be stored in coded form and be retrieved for a configuration and adaptation of the semiconductor memory device.
摘要翻译：因此，根据本发明，可以对于不同的可能的工作频率来最佳地使用半导体存储器件，形成寄存器区域，其中关于当前工作频率的频率信息可以被编码形式存储并被检索用于配置以及半导体存储器件的适配。

7. 发明授权

US08098086B2 Integrated circuit and programmable delay 有权
标题翻译：集成电路和可编程延时
公开(公告)号：US08098086B2
公开(公告)日：2012-01-17
申请号：US12939468
申请日：2010-11-04
申请人： Kazimierz Szczypinski
发明人： Kazimierz Szczypinski
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , G11C7/22 , G11C7/222 , H03K5/133 , H03K2005/00104 , H03K2005/00123 , H03K2005/00241
摘要： Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element.
摘要翻译：集成电路和可编程延时。一个实施例提供了包括具有多个单个延迟单元的可编程延迟元件的集成电路。延迟单元包括第一输入和第二输入以及第一输出。延迟单元被布置成形成链，使得先前延迟单元的第一输出耦合到连续延迟单元的第二输入。任何延迟单元的第一输入被配置为接收待延迟的输入信号。多个延迟单元中的延迟单元被配置为构成包括布置在起始点下游的任何延迟单元的信号路径的起始点。链中最后一个延迟单元的第一个输出形成可编程延迟元件的输出。

8. 发明申请

US20110057699A1 INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY 有权
标题翻译：集成电路和可编程延迟
公开(公告)号：US20110057699A1
公开(公告)日：2011-03-10
申请号：US12939468
申请日：2010-11-04
申请人： Kazimierz Szczypinski
发明人： Kazimierz Szczypinski
IPC分类号： H03L7/00 , H03H11/26
CPC分类号： H03K5/135 , G11C7/22 , G11C7/222 , H03K5/133 , H03K2005/00104 , H03K2005/00123 , H03K2005/00241
摘要： Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element.
摘要翻译：集成电路和可编程延迟。一个实施例提供了包括具有多个单个延迟单元的可编程延迟元件的集成电路。延迟单元包括第一输入和第二输入以及第一输出。延迟单元被布置成形成链，使得先前延迟单元的第一输出耦合到连续延迟单元的第二输入。任何延迟单元的第一输入被配置为接收待延迟的输入信号。多个延迟单元中的延迟单元被配置为构成包括布置在起始点下游的任何延迟单元的信号路径的起始点。链中最后一个延迟单元的第一个输出形成可编程延迟元件的输出。

9. 发明申请

US20100045351A1 INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY 有权
标题翻译：集成电路和可编程延迟
公开(公告)号：US20100045351A1
公开(公告)日：2010-02-25
申请号：US12195120
申请日：2008-08-20
申请人： Kazimierz Szczypinski
发明人： Kazimierz Szczypinski
IPC分类号： H03L7/00 , H03H11/26 , H03K3/00
CPC分类号： H03K5/135 , G11C7/22 , G11C7/222 , H03K5/133 , H03K2005/00104 , H03K2005/00123 , H03K2005/00241
摘要： Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element.
摘要翻译：集成电路和可编程延时。一个实施例提供了包括具有多个单个延迟单元的可编程延迟元件的集成电路。延迟单元包括第一输入和第二输入以及第一输出。延迟单元被布置成形成链，使得先前延迟单元的第一输出耦合到连续延迟单元的第二输入。任何延迟单元的第一输入被配置为接收待延迟的输入信号。多个延迟单元中的延迟单元被配置为构成包括布置在起始点下游的任何延迟单元的信号路径的起始点。链中最后一个延迟单元的第一个输出形成可编程延迟元件的输出。

10. 发明申请

US20090251206A1 INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US20090251206A1
公开(公告)日：2009-10-08
申请号：US12061812
申请日：2008-04-03
申请人： Kazimierz Szczypinski , Weng-Ming Lee
发明人： Kazimierz Szczypinski , Weng-Ming Lee
IPC分类号： H01L21/441 , H01L25/00
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C11/4093
摘要： An integrated circuit comprising at least one signal path which is adapted to route at least one signal from an origin to a target block, said signal path comprising at least an adjustable driver circuit comprising an input and an output, which is adapted to receive an electric signal having a first signal power as an input signal and which is adapted to provide an electric signal having a second signal power as an output signal is provided. Furthermore, the integrated circuit comprises at least one interconnect having an ohmic resistance and an electric capacity and being adapted to route said electric signal having a second signal power to said target block. Furthermore, a method for manufacturing such an integrated circuit is provided.
摘要翻译：一种集成电路，包括至少一个信号路径，其适于将至少一个信号从原点路由到目标块，所述信号路径至少包括可调节驱动器电路，其包括输入和输出，其适于接收电提供具有第一信号功率作为输入信号并且适于提供具有第二信号功率的电信号作为输出信号的信号。此外，集成电路包括具有欧姆电阻和电容的至少一个互连，并且适于将具有第二信号功率的所述电信号路由到所述目标块。此外，提供了一种用于制造这种集成电路的方法。

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