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1. 发明申请

US20110314259A1 OPERATING A STACK OF INFORMATION IN AN INFORMATION HANDLING SYSTEM 有权
标题翻译：在信息处理系统中操作信息堆栈
公开(公告)号：US20110314259A1
公开(公告)日：2011-12-22
申请号：US12817609
申请日：2010-06-17
申请人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , IL Park
发明人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , IL Park
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30134 , G06F9/30163 , G06F9/3861
摘要： A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.
摘要翻译：一个指针用于指向一堆信息中的下一个读取位置。将信息推送到堆栈中：保存指针的值，该指针指向堆栈内的第一个位置作为下一个读取位置; 指针被更新，使得它指向堆栈内的第二位置作为下一个读取位置; 并且将信息写入第二位置处的存储。为了从堆栈弹出信息：响应于指针，从第二位置读取信息作为下一个读取位置; 并且指针被恢复为等于保存的值，使得其指向作为下一个读取位置的第一位置。

2. 发明授权

US08943299B2 Operating a stack of information in an information handling system 有权
标题翻译：在信息处理系统中操作一堆信息
公开(公告)号：US08943299B2
公开(公告)日：2015-01-27
申请号：US12817609
申请日：2010-06-17
申请人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , Il Park
发明人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , Il Park
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30134 , G06F9/30163 , G06F9/3861
摘要： A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.
摘要翻译：一个指针用于指向一堆信息中的下一个读取位置。将信息推送到堆栈中：保存指针的值，该指针指向堆栈内的第一个位置作为下一个读取位置; 指针被更新，使得它指向堆栈内的第二位置作为下一个读取位置; 并且将信息写入第二位置处的存储。为了从堆栈弹出信息：响应于指针，从第二位置读取信息作为下一个读取位置; 并且指针被恢复为等于保存的值，使得其指向作为下一个读取位置的第一位置。

3. 发明授权

US09069563B2 Reducing store-hit-loads in an out-of-order processor 有权
标题翻译：减少无序处理器中的存储命中负载
公开(公告)号：US09069563B2
公开(公告)日：2015-06-30
申请号：US13235174
申请日：2011-09-16
申请人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
发明人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3834 , G06F9/3838
摘要： A technique for reducing store-hit-loads in an out-of-order processor includes storing a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry. In response to detecting another SHL pipeline flush for the store address, a current count associated with the SHL entry is updated. In response to the current count associated with the SHL entry reaching a first terminal count, a dependency for the store instruction is created such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes.
摘要翻译：用于减少无序处理器中的存储命中负载的技术包括存储与存储命中加载（SHL）管线冲洗相关联的存储指令的存储地址在SHL条目中。响应于检测存储地址的另一个SHL管道flush，更新与SHL条目相关联的当前计数。响应于与SHL条目相关联的当前计数到达第一终端计数，创建存储指令的依赖关系，使得具有与存储地址重叠的加载地址的较年轻加载指令的执行停止，直到存储指令执行。

4. 发明申请

US20130073833A1 REDUCING STORE-HIT-LOADS IN AN OUT-OF-ORDER PROCESSOR 有权
标题翻译：减少订单处理器中的存储负载
公开(公告)号：US20130073833A1
公开(公告)日：2013-03-21
申请号：US13235174
申请日：2011-09-16
申请人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
发明人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3834 , G06F9/3838
摘要： A technique for reducing store-hit-loads in an out-of-order processor includes storing a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry. In response to detecting another SHL pipeline flush for the store address, a current count associated with the SHL entry is updated. In response to the current count associated with the SHL entry reaching a first terminal count, a dependency for the store instruction is created such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes.
摘要翻译：用于减少无序处理器中的存储命中负载的技术包括存储与存储命中加载（SHL）管线冲洗相关联的存储指令的存储地址在SHL条目中。响应于检测存储地址的另一个SHL管道flush，更新与SHL条目相关联的当前计数。响应于与SHL条目相关联的当前计数到达第一终端计数，创建存储指令的依赖关系，使得具有与存储地址重叠的加载地址的较年轻加载指令的执行停止，直到存储指令执行。

5. 发明申请

US20120005462A1 Hardware Assist for Optimizing Code During Processing 审中-公开
标题翻译：处理过程中优化代码的硬件辅助
公开(公告)号：US20120005462A1
公开(公告)日：2012-01-05
申请号：US12828697
申请日：2010-07-01
申请人： Ronald P. Hall , Brian R. Konigsburg , David S. Levitan , Brian R. Mestan
发明人： Ronald P. Hall , Brian R. Konigsburg , David S. Levitan , Brian R. Mestan
IPC分类号： G06F9/38
CPC分类号： G06F11/3466 , G06F9/3808 , G06F9/3844 , G06F11/348 , G06F2201/88
摘要： A method, data processing system, and computer program product for obtaining information about instructions. Instructions are processed. In response to processing a branch instruction in the instructions, a determination is made as to whether a result from processing the branch instruction follows a prediction of whether a branch is predicted to occur for the branch instruction. In response to the result following the prediction, the branch instruction is added to a current segment in a trace. In response to an absence of the result following the prediction, the branch instruction is added to the current segment in the trace and a first new segment and a second new segment are created. The first new segment includes a first branch instruction reached in the instructions from following the prediction. The second new segment includes a second branch instruction in the instructions reached from not following the prediction.
摘要翻译：一种用于获取关于指令的信息的方法，数据处理系统和计算机程序产品。处理说明。响应于在指令中处理分支指令，确定来自处理分支指令的结果是否遵循预测分支指令是否为分支指令发生的预测。响应于预测结果，分支指令被添加到跟踪中的当前段。响应于预测之后没有结果，分支指令被添加到跟踪中的当前段，并且创建第一新段和第二新段。第一个新的段包括在跟随预测的指令中达到的第一个分支指令。第二个新的段包括从不遵循预测到达的指令中的第二个分支指令。

6. 发明申请

US20100031011A1 METHOD AND APPARATUS FOR OPTIMIZED METHOD OF BHT BANKING AND MULTIPLE UPDATES 审中-公开
标题翻译：用于BHT银行优化方法和多种更新的方法和装置
公开(公告)号：US20100031011A1
公开(公告)日：2010-02-04
申请号：US12185776
申请日：2008-08-04
申请人： Lei Chen , David S. Levitan , David Mui , Robert A. Philhower
发明人： Lei Chen , David S. Levitan , David Mui , Robert A. Philhower
IPC分类号： G06F9/30
CPC分类号： G06F9/3806
摘要： The invention relates to a method and apparatus for controlling the instruction flow in a computer system and more particularly to the predicting of outcome of branch instructions using branch prediction arrays, such as BHTs. In an embodiment, the invention allows concurrent BHT read and write accesses without the need for a multi-ported BHT design, while still providing comparable performance to that of a multi-ported BHT design.
摘要翻译：本发明涉及一种用于控制计算机系统中的指令流的方法和装置，更具体地说，涉及使用诸如BHT之类的分支预测数组来预测分支指令的结果。在一个实施例中，本发明允许并行BHT读和写访问，而不需要多端口BHT设计，同时仍然提供与多端口BHT设计的性能相当的性能。

7. 发明申请

US20130055033A1 HARDWARE-ASSISTED PROGRAM TRACE COLLECTION WITH SELECTABLE CALL-SIGNATURE CAPTURE 审中-公开
标题翻译：硬件辅助程序跟踪采集与可选择的呼叫签名捕获
公开(公告)号：US20130055033A1
公开(公告)日：2013-02-28
申请号：US13300863
申请日：2011-11-21
申请人： Giles R. Frazier , David S. Levitan , Brian R. Mestan , Mauricio J. Serrano
发明人： Giles R. Frazier , David S. Levitan , Brian R. Mestan , Mauricio J. Serrano
IPC分类号： G06F11/34
CPC分类号： G06F11/3466 , G06F11/348 , G06F11/3636 , G06F2201/83 , G06F2201/865
摘要： Hardware-assisted program tracing is facilitated by a processor that includes a root instruction address register, a program trace signature computation unit and a call signature register. When a program instruction having an address matching the root instruction address register is executed, a program trace signature is captured in the call signature register and capture of branch history is commenced. By accumulating different values of the call signature register, for example in response to an interrupt generated when the root instruction is executed, software that performs program tracing can obtain signatures of all of the multiple execution paths that lead to the root instruction, which is also specified by software in order to set different root instructions for program tracing. In an alternative implementation, a storage for multiple call signatures is provided in the processor and read at once by the software.
摘要翻译：硬件辅助程序跟踪由包括根指令地址寄存器，程序跟踪签名计算单元和呼叫签名寄存器的处理器来促进。当执行具有与根指令地址寄存器匹配的地址的程序指令时，在呼叫签名寄存器中捕获程序跟踪签名，并且开始分支历史记录的捕获。通过累积呼叫签名寄存器的不同值，例如响应于执行根指令时产生的中断，执行程序跟踪的软件可以获得导致根指令的所有多个执行路径的签名，这也是由软件指定，以便为程序跟踪设置不同的根指令。在替代实现中，在处理器中提供用于多个呼叫签名的存储器，并由软件一次读取。

8. 发明授权

US07844807B2 Branch target address cache storing direct predictions 失效
标题翻译：分支目标地址缓存存储直接预测
公开(公告)号：US07844807B2
公开(公告)日：2010-11-30
申请号：US12024197
申请日：2008-02-01
申请人： David S. Levitan , Lixin Zhang
发明人： David S. Levitan , Lixin Zhang
IPC分类号： G06F9/35 , G06F9/355 , G06F9/40
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3844
摘要： In at least one embodiment, a processor includes at least one execution unit and instruction sequencing logic that fetches instructions for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address cache (BTAC) having at least one direct entry providing storage for a direct branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address immediately after the first instruction fetch address and at least one indirect entry providing storage for an indirect branch target address prediction associating a third instruction fetch address with a branch target address to be used as a fourth instruction fetch address subsequent to both the third instruction fetch address and an intervening fifth instruction fetch address.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元和指令排序逻辑，其提取由执行单元执行的指令。指令排序逻辑包括分支逻辑，该分支逻辑输出用作指令获取地址的预测分支目标地址。分支逻辑包括分支目标地址高速缓存（BTAC），其具有至少一个直接条目，为直接分支目标地址预测提供存储，该直接分支目标地址预测将第一指令获取地址与分支目标地址相关联，以将分配目标地址紧随在第二指令获取地址之后第一指令获取地址和至少一个间接条目提供用于间接分支目标地址预测的存储，用于将第三指令获取地址与分支目标地址相关联，以将分配目标地址用作第三指令提取地址和中间地址之后的第四指令获取地址第五指令提取地址。

9. 发明授权

US07809933B2 System and method for optimizing branch logic for handling hard to predict indirect branches 有权
标题翻译：用于优化分支逻辑以处理难以预测间接分支的系统和方法
公开(公告)号：US07809933B2
公开(公告)日：2010-10-05
申请号：US11759350
申请日：2007-06-07
申请人： David S. Levitan , Wolfram Sauer
发明人： David S. Levitan , Wolfram Sauer
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/322 , G06F9/30181 , G06F9/3804
摘要： A system and method for optimizing the branch logic of a processor to improve handling of hard to predict indirect branches are provided. The system and method leverage the observation that there will generally be only one move to the count register (mtctr) instruction that will be executed while a branch on count register (bcctr) instruction has been fetched and not executed. With the mechanisms of the illustrative embodiments, fetch logic detects that it has encountered a bcctr instruction that is hard to predict and, in response to this detection, blocks the target fetch from entering the instruction buffer of the processor. At this point, the fetch logic has fetched all the instructions up to and including the bcctr instruction but no target instructions. When the next mtctr instruction is executed, the branch logic of the processor grabs the data and starts fetching using that target address. Since there are no other target instructions that were fetched, no flush is needed if that target address is the correct address, i.e. the branch prediction is correct.
摘要翻译：提供了一种用于优化处理器的分支逻辑以改善难以预测间接分支的处理的系统和方法。系统和方法利用这样的观察，通常只有一个移动到计数寄存器（mtctr）指令，在计数寄存器（bcctr）指令的分支已经被取出并且不被执行时将被执行。利用说明性实施例的机制，提取逻辑检测到它已经遇到难以预测的bcctr指令，并且响应于该检测阻止目标提取进入处理器的指令缓冲器。此时，提取逻辑已经获取了直到并包括bcctr指令但没有目标指令的所有指令。当执行下一个mtctr指令时，处理器的分支逻辑抓取数据，并使用该目标地址开始提取。由于没有其他目标指令被取出，如果目标地址是正确的地址，即分支预测是正确的，则不需要刷新。

10. 发明授权

US5465373A Method and system for single cycle dispatch of multiple instructions in a superscalar processor system 失效
标题翻译：用于超标量处理器系统中多个指令的单周期调度的方法和系统
公开(公告)号：US5465373A
公开(公告)日：1995-11-07
申请号：US1864
申请日：1993-01-08
申请人： James A. Kahle , Chin-Cheng Kau , David S. Levitan , Aubrey D. Ogden , Ali A. Poursepanj , Paul K.-G. Tu , Donald E. Waldecker
发明人： James A. Kahle , Chin-Cheng Kau , David S. Levitan , Aubrey D. Ogden , Ali A. Poursepanj , Paul K.-G. Tu , Donald E. Waldecker
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/384
摘要： A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register.
摘要翻译：一种用于在超标量处理器系统中允许单周期指令调度的方法和系统，其将多个指令同时分配到一组执行单元以执行并将其结果放置在指定的通用寄存器内。每个指令通常包括至少一个源操作数和一个目的操作数。提供多个中间存储缓冲器，并且每当将指令分派到可用执行单元时，中间存储缓冲器中的特定一个被分配给调度指令内的任何目的地操作数，允许在单个周期内发送指令通过消除对确定和选择指定的通用寄存器或指定的备用通用寄存器的任何要求。

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