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1. 发明授权

US5465373A Method and system for single cycle dispatch of multiple instructions in a superscalar processor system 失效
标题翻译：用于超标量处理器系统中多个指令的单周期调度的方法和系统
公开(公告)号：US5465373A
公开(公告)日：1995-11-07
申请号：US1864
申请日：1993-01-08
申请人： James A. Kahle , Chin-Cheng Kau , David S. Levitan , Aubrey D. Ogden , Ali A. Poursepanj , Paul K.-G. Tu , Donald E. Waldecker
发明人： James A. Kahle , Chin-Cheng Kau , David S. Levitan , Aubrey D. Ogden , Ali A. Poursepanj , Paul K.-G. Tu , Donald E. Waldecker
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/384
摘要： A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register.
摘要翻译：一种用于在超标量处理器系统中允许单周期指令调度的方法和系统，其将多个指令同时分配到一组执行单元以执行并将其结果放置在指定的通用寄存器内。每个指令通常包括至少一个源操作数和一个目的操作数。提供多个中间存储缓冲器，并且每当将指令分派到可用执行单元时，中间存储缓冲器中的特定一个被分配给调度指令内的任何目的地操作数，允许在单个周期内发送指令通过消除对确定和选择指定的通用寄存器或指定的备用通用寄存器的任何要求。

2. 发明授权

US5491829A Method and system for indexing the assignment of intermediate storage buffers in a superscalar processor system 失效
标题翻译：用于索引超标量处理器系统中的中间存储缓冲区的分配的方法和系统
公开(公告)号：US5491829A
公开(公告)日：1996-02-13
申请号：US438819
申请日：1995-05-11
申请人： Chin-Cheng Kau , Aubrey D. Ogden , Donald E. Waldecker
发明人： Chin-Cheng Kau , Aubrey D. Ogden , Donald E. Waldecker
IPC分类号： G06F9/38 , G06F9/28
CPC分类号： G06F9/3836 , G06F9/384
摘要： A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having a plurality of intermediate storage buffers, a plurality of general purpose registers, and a storage buffer index. Multiple scalar instructions may be simultaneously dispatched from a dispatch buffer to a plurality of execution units. Each of the multiple scalar instructions generally include at least one source operand and one destination operand. A particular one of the plurality of intermediate storage buffers is assigned to a destination operand within a selected one of the multiple scalar instructions. A relationship between the particular one of the plurality of intermediate storage buffers and a designated one of the plurality of general purpose registers is stored in the storage buffer index at that time when the instruction which has been dispatched is replaced in the dispatcher by another instruction in the application program sequence. Results of execution from the selected one of the multiple scalar instructions are stored in the particular one of the intermediate storage buffers when the selected instruction is executed. The storage buffer index is used to determine which storage buffers to use as source operands for those instructions which are dispatched between the time that a storage buffer has been assigned for a specific general purpose register and the results of execution are moved from the storage buffer into the general purpose register.
摘要翻译：一种用于在具有多个中间存储缓冲器，多个通用寄存器和存储缓冲器索引的超标量处理器系统中增强指令调度效率的方法和系统。可以将多个标量指令从调度缓冲器同时分派到多个执行单元。多个标量指令中的每一个通常包括至少一个源操作数和一个目的操作数。多个中间存储缓冲器中的特定一个被分配给多个标量指令中所选择的一个中的目的地操作数。多个中间存储缓冲器中的特定一个和多个通用寄存器中的一个指定的一个通用寄存器之间的关系被存储在存储缓冲器索引中，当已经发送的指令在调度器中被另一个指令替换时应用程序序列。当执行所选择的指令时，从所选择的多个标量指令中执行的结果被存储在特定的一个中间存储缓冲器中。存储缓冲器索引用于确定哪些存储缓冲区用作在为特定通用寄存器分配存储缓冲区和执行结果的时间之间调度的那些指令的源操作数，并将执行结果从存储缓冲区移动到通用寄存器。

3. 发明授权

US5341502A Device for assigning a shared resource in a data processing system 失效
标题翻译：用于在数据处理系统中分配共享资源的装置
公开(公告)号：US5341502A
公开(公告)日：1994-08-23
申请号：US989864
申请日：1992-12-14
申请人： Anita S. Grossman , Chin-Cheng Kau , Aubrey D. Ogden , Mason L. Weems
发明人： Anita S. Grossman , Chin-Cheng Kau , Aubrey D. Ogden , Mason L. Weems
IPC分类号： G06F9/50 , G06F13/14 , G06F12/02
CPC分类号： G06F9/5011 , G06F13/14 , G06F2209/503 , G06F2209/507
摘要： In accordance with the present invention, a resource allocation array has at least one resource input line (Aj), at least one request for resource input line (Ri) and at least one cell (12) coupled to the at least one resource input line and to the at least one request for resource line. The resource allocation array assigns one resource to one request for the resource. The one resource and the one request for the resource are both of a group of at least one resource and of a group of at least one request for the resource, respectively. The availability and unavailability of the resource is represented by a first and a second predetermined resource signal, respectively. The assertion and non assertion of the request for resource is represented by a third and a fourth predetermined request for resource signal, respectively. The at least one resource input line is associated with one of the at least one resource signals. The at least one request for resource input line is associated with one of the at least one request for resource signals. The cell generates a predetermined signal, toggles the resource signal from the first to the second predetermined resource signal, and toggles the request for resource signal from the third to the fourth predetermined request for resource signal if the one resource signal and the one request for resource signal correspond in logic state to the first and to the third predetermined signals, respectively.
摘要翻译：根据本发明，资源分配阵列具有至少一个资源输入线（Aj），至少一个资源输入线（R1）的请求以及耦合到该至少一个资源输入线的至少一个小区（12）以及至少一个资源线路请求。资源分配阵列为资源的一个请求分配一个资源。资源的一个资源和一个请求分别是至少一个资源的组和至少一个资源请求的组。资源的可用性和不可用性分别由第一和第二预定资源信号表示。资源请求的断言和非断言分别由资源信号的第三和第四预定请求表示。所述至少一个资源输入线与所述至少一个资源信号中的一个相关联。对资源输入线的至少一个请求与至少一个资源信号请求中的一个相关联。小区产生预定信号，切换从第一预定资源信号到第二预定资源信号的资源信号，并且如果一个资源信号和一个资源请求，则将资源信号的请求从第三到第四预定资源信号请求切换信号分别对应于第一和第三预定信号的逻辑状态。

4. 发明授权

US5467473A Out of order instruction load and store comparison 失效
标题翻译：无序指令加载和存储比较
公开(公告)号：US5467473A
公开(公告)日：1995-11-14
申请号：US1976
申请日：1993-01-08
申请人： James A. Kahle , Chin-Cheng Kau
发明人： James A. Kahle , Chin-Cheng Kau
IPC分类号： G06F9/38
CPC分类号： G06F9/3834
摘要： A processing system allows for out of order instruction execution and includes at least one load/store unit for loading instructions to a register for processing by a fixed point unit, floating point unit, or the like, and store the results to memory. A load queue maintains the addresses and program numbers of the load instructions. During execution the address of the store instruction is compared to the address in the load queue of previously executed load instructions. A program counter compares the program number of the store instruction with the program number of the load instruction in the load queue. If the addresses are different, then no impermissible out of order situation exists between the load and store instructions being compared, because the data is not at the same address. If the address is the same, and the store program number is greater than the load program number, then the instructions have been executed in order (the load correctly preceded the store) and no problem exists. However, if the addresses are the same and the load instruction has been incorrectly reordered to precede the store instruction, then a reordering conflict exists and the load instructions must be re-executed.
摘要翻译：处理系统允许执行不一致的指令，并且包括至少一个加载/存储单元，用于将指令加载到寄存器以由固定点单元，浮点单元等进行处理，并将结果存储到存储器中。加载队列维护加载指令的地址和程序号。在执行期间，将存储指令的地址与先前执行的加载指令的加载队列中的地址进行比较。程序计数器将存储指令的程序号与加载队列中的加载指令的程序号进行比较。如果地址不同，那么由于数据不在相同的地址，所以在被比较的加载和存储指令之间不存在无序的情况。如果地址相同，并且存储程序号大于加载程序号，则指令已按顺序执行（加载正确存储在存储之前），并且不存在问题。然而，如果地址相同并且加载指令已被错误地重新排序到存储指令之前，则存在重新排序冲突，并且必须重新执行加载指令。

5. 发明授权

US5898882A Method and system for enhanced instruction dispatch in a superscalar processor system utilizing independently accessed intermediate storage 失效
标题翻译：利用独立访问的中间存储器在超标量处理器系统中增强指令调度的方法和系统
公开(公告)号：US5898882A
公开(公告)日：1999-04-27
申请号：US1865
申请日：1993-01-08
申请人： James Allan Kahle , Chin-Cheng Kau , Aubrey Deene Ogden , Ali Asghar Poursepanj , Paul Kang-Guo Tu , Donald Emil Waldecker
发明人： James Allan Kahle , Chin-Cheng Kau , Aubrey Deene Ogden , Ali Asghar Poursepanj , Paul Kang-Guo Tu , Donald Emil Waldecker
IPC分类号： G06F9/38 , G06F15/16
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855
摘要： A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register.
摘要翻译：一种用于在超标量处理器系统中允许单周期指令调度的方法和系统，其将多个指令同时分配到一组执行单元以执行并将其结果放置在指定的通用寄存器内。每个指令通常包括至少一个源操作数和一个目的操作数。提供多个中间存储缓冲器，并且每当将指令分派到可用执行单元时，中间存储缓冲器中的特定一个被分配给调度指令内的任何目的地操作数，允许在单个周期内发送指令通过消除对确定和选择指定的通用寄存器或指定的备用通用寄存器的任何要求。

6. 发明授权

US5764942A Method and system for selective serialization of instruction processing in a superscalar processor system 失效
标题翻译：用于在超标量处理器系统中选择性地串行化指令处理的方法和系统
公开(公告)号：US5764942A
公开(公告)日：1998-06-09
申请号：US689437
申请日：1996-08-12
申请人： James Allan Kahle , Chin-Cheng Kau , Aubrey Deene Ogden , Ali Asghar Poursepanj , Paul Kang-Guo Tu , Donald Emil Waldecker
发明人： James Allan Kahle , Chin-Cheng Kau , Aubrey Deene Ogden , Ali Asghar Poursepanj , Paul Kang-Guo Tu , Donald Emil Waldecker
IPC分类号： G06F9/38 , G06F9/30 , G06F9/312
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3855
摘要： The method and system of the present invention permits enhanced instruction dispatch efficiency in a superscalar processor system capable of fetching an application specified ordered sequence of scalar instructions and simultaneously dispatching a group of the scalar instructions to a plurality of execution units on a nonsequential opportunistic basis. A group of scalar instructions fetched in an application specified ordered sequence on a nonsequential opportunistic basis is processed in the present invention. The present invention detects conditions requiring serialization during the processing. In response to a detection of a condition requiring serialization, processing of particular scalar instructions from the group of scalar instructions are selectively controlled, wherein at least a portion of the scalar instructions within the group of scalar instructions are thereafter processed in a serial fashion.
摘要翻译：本发明的方法和系统允许在能够提取应用指定的标量指令的有序序列的超标量处理器系统中增强指令调度效率，并且以非顺序的机会主义的方式在多个执行单元上同时分派一组标量指令。在本发明中处理以应用程序指定的顺序序列在非顺序机会性基础上提取的一组标量指令。本发明检测在处理期间需要串行化的条件。响应于需要串行化的条件的检测，选择性地控制来自标准指令组的特定标量指令的处理，其中标量指令组中的标量指令的至少一部分此后以串行方式被处理。

7. 发明授权

US5978896A Method and system for increased instruction dispatch efficiency in a superscalar processor system 失效
标题翻译：用于在超标量处理器系统中提高指令调度效率的方法和系统
公开(公告)号：US5978896A
公开(公告)日：1999-11-02
申请号：US289801
申请日：1994-08-12
申请人： James Allan Kahle , Chin-Cheng Kau , David Steven Levitan , Aubrey Deene Ogden
发明人： James Allan Kahle , Chin-Cheng Kau , David Steven Levitan , Aubrey Deene Ogden
IPC分类号： G06F9/38
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3885
摘要： A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatching instructions from an associated instruction buffer to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer, the remaining instructions are shifted within the instruction buffer in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer from the instruction queue utilizing a selectively controlled multiplex circuit. In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.
摘要翻译：一种用于在具有指令队列的超标量处理器系统中提高指令调度效率的方法和系统，所述指令队列用于以应用指定的顺序顺序接收一组指令，以及指令调度单元，用于将指令从相关联的指令缓冲器分派到多个执行单元，基础。周期性地确定关联指令缓冲器内的指令的调度状态，并且响应于在指令缓冲器的开始处的指令的调度，剩余的指令在应用指定的顺序顺序的指令缓冲器内移动，部分组的指令通过选择性控制的多路复用电路从指令队列加载到指令缓冲器中。以这种方式，可以将附加指令分派到可用的执行单元，而不需要完全调度先前的指令组。

8. 发明授权

US5765221A Method and system of addressing which minimize memory utilized to store logical addresses by storing high order bits within a register 失效
标题翻译：寻址方法和系统，通过在寄存器中存储高阶位来最小化用于存储逻辑地址的存储器
公开(公告)号：US5765221A
公开(公告)日：1998-06-09
申请号：US767568
申请日：1996-12-16
申请人： Paul Charles Rossbach , Chin-Cheng Kau , David Stephen Levitan
发明人： Paul Charles Rossbach , Chin-Cheng Kau , David Stephen Levitan
IPC分类号： G06F9/32 , G06F9/355 , G06F9/38 , G06F12/04
CPC分类号： G06F9/342 , G06F9/30094 , G06F9/32 , G06F9/321 , G06F9/324 , G06F9/3557 , G06F9/3802
摘要： An improved method of addressing within a pipelined processor having an address bit width of m+n bits is disclosed, which includes storing m high order bits corresponding to a first range of addresses, which encompasses a selected plurality of data executing within the pipelined processor. The n low order bits of addresses associated with each of the selected plurality of data are also stored. After determining the address of a subsequent datum to be executed within the processor, the subsequent datum is fetched. In response to fetching a subsequent datum having an address outside of the first range of addresses, a status register is set to a first of two states to indicate that an update to the first address register is required. In response to the status register being set to the second of the two states, the subsequent datum is dispatched for execution within the pipelined processor. The n low order bits of the subsequent datum are then stored, such that memory required to store addresses of instructions executing within the pipelined processor is thereby decreased.
摘要翻译：公开了一种具有地址位宽度为m + n位的流水线处理器内的寻址改进方法，其包括存储对应于第一地址范围的m个高位，其包含在流水线处理器内执行的选定的多个数据。还存储与所选择的多个数据中的每一个相关联的n个低位地址。在确定要在处理器中执行的后续数据的地址之后，获取随后的数据。响应于获取具有在第一地址范围之外的地址的后续数据，状态寄存器被设置为两种状态中的第一状态，以指示需要对第一地址寄存器的更新。响应于将状态寄存器设置为两个状态中的第二个状态，随后的数据被调度以在流水线处理器内执行。然后存储随后数据的n个低位，从而减少了在流水线处理器内执行的指令的存储地址所需的存储器。

9. 发明授权

US5761473A Method and system for increased instruction synchronization efficiency in a superscalar processsor system utilizing partial data dependency interlocking 失效
标题翻译：使用部分数据依赖互锁的超标量过程系统中提高指令同步效率的方法和系统
公开(公告)号：US5761473A
公开(公告)日：1998-06-02
申请号：US1863
申请日：1993-01-08
申请人： James Allan Kahle , Chin-Cheng Kau
发明人： James Allan Kahle , Chin-Cheng Kau
IPC分类号： G06F9/38 , G06F9/345
CPC分类号： G06F9/3838
摘要： A method and system for increased instruction synchronization efficiency in a superscalar processor system which includes instructions having multiple source and destination operands. Simultaneous dispatching of multiple instructions creates a source-to-destination data dependency problem in that the results of one instruction may be necessary to accomplish execution of a second instruction. Data dependency hazards may be eliminated by prohibiting each instruction from dispatching until all possible data dependencies have been eliminated by the completion of preceding instructions; however, instruction dispatch efficiency is substantially decreased utilizing this technique. Data dependency interlock circuitry may be utilized to clear possible data dependency hazards; however, the complexity of such circuitry increases dramatically as the number of interlocked sources and destinations increases. The method and system of the present invention utilizes data dependency interlock circuitry capable of interlocking two source operands by two destination operands for each instruction. Instructions having three or more source operands are interlocked at the dispatch stage for the first two source operands utilizing existing data dependency interlock circuitry. Thereafter, the instruction is dispatched only after data dependency hazards are cleared for the first two source operands, utilizing the data dependency interlock circuitry, and all instructions preceding the instruction have been completed, eliminating possible data dependency hazards for the third source operand. In this manner, instructions which include three source operands may be synchronized without requiring a substantial increase in data dependency interlock circuitry and with only a slight degradation in system efficiency.
摘要翻译：一种用于在包括具有多个源和目的地操作数的指令的超标量处理器系统中提高指令同步效率的方法和系统。多个指令的同时调度会产生源对目标数据依赖性问题，因为一个指令的结果可能需要完成第二个指令的执行。可以通过禁止每个指令进行调度直到所有可能的数据相关性已经通过完成前面的指令而被消除来消除数据依赖危害; 然而，利用这种技术，指令调度效率显着降低。可以利用数据依赖互锁电路来清除可能的数据依赖危害; 然而，随着互锁源和目的地的数量的增加，这种电路的复杂性急剧增加。本发明的方法和系统利用数据相关互锁电路，其能够通过用于每个指令的两个目的地操作数来互锁两个源操作数。具有三个或更多个源操作数的指令在使用现有数据依赖性互锁电路的前两个源操作数的调度阶段互锁。此后，只有在前两个源操作数的数据依赖性危险被清除之后，才使用数据相关联锁电路来调度指令，并且完成了指令之前的所有指令，从而消除了对第三源操作数的可能的数据依赖性危害。以这种方式，包括三个源操作数的指令可以被同步，而不需要数据依赖性联锁电路的显着增加，并且只有系统效率的轻微降低。

10. 发明授权

US06452592B2 Clock generation for sampling analog video 失效
标题翻译：用于采样模拟视频的时钟生成
公开(公告)号：US06452592B2
公开(公告)日：2002-09-17
申请号：US09863239
申请日：2001-05-21
申请人： Biao Zhang , Chin-Cheng Kau
发明人： Biao Zhang , Chin-Cheng Kau
IPC分类号： G09G500
CPC分类号： G09G5/008
摘要： A method and circuit generates a sampling clock signal that digitizes an analog video signal. The sampling clock signal is generated by a clock divider coupled to the horizontal synchronization signal of the analog video signal. A divisor calculator calculates a divisor for the clock divider to control the frequency of the sampling clock signal. Specifically, the divisor calculator selects an initial divisor for the clock divider. Then the divisor calculator calculates a new divisor based on the target pixel value provided by a mode detector and the measured pixel value from a counter. Some embodiments of the present invention provides fine tuning of the frequency by testing other possible divisors with a plurality of different phases. In addition, some embodiments of the present invention calibrate the phase of the sampling clock signal to generate a phase shifted sampling clock signal.
摘要翻译：方法和电路产生对模拟视频信号进行数字化的采样时钟信号。采样时钟信号由耦合到模拟视频信号的水平同步信号的时钟分频产生。除数计算器计算时钟分频器的除数以控制采样时钟信号的频率。具体来说，除数计算器选择时钟分频器的初始除数。然后，除数计算器基于由模式检测器提供的目标像素值和来自计数器的测量像素值来计算新的除数。本发明的一些实施例通过测试具有多个不同相位的其它可能因数来提供频率的微调。此外，本发明的一些实施例校准采样时钟信号的相位以产生相移采样时钟信号。

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