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1. 发明申请

US20110314259A1 OPERATING A STACK OF INFORMATION IN AN INFORMATION HANDLING SYSTEM 有权
标题翻译：在信息处理系统中操作信息堆栈
公开(公告)号：US20110314259A1
公开(公告)日：2011-12-22
申请号：US12817609
申请日：2010-06-17
申请人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , IL Park
发明人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , IL Park
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30134 , G06F9/30163 , G06F9/3861
摘要： A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.
摘要翻译：一个指针用于指向一堆信息中的下一个读取位置。将信息推送到堆栈中：保存指针的值，该指针指向堆栈内的第一个位置作为下一个读取位置; 指针被更新，使得它指向堆栈内的第二位置作为下一个读取位置; 并且将信息写入第二位置处的存储。为了从堆栈弹出信息：响应于指针，从第二位置读取信息作为下一个读取位置; 并且指针被恢复为等于保存的值，使得其指向作为下一个读取位置的第一位置。

2. 发明授权

US08943299B2 Operating a stack of information in an information handling system 有权
标题翻译：在信息处理系统中操作一堆信息
公开(公告)号：US08943299B2
公开(公告)日：2015-01-27
申请号：US12817609
申请日：2010-06-17
申请人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , Il Park
发明人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , Il Park
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30134 , G06F9/30163 , G06F9/3861
摘要： A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.
摘要翻译：一个指针用于指向一堆信息中的下一个读取位置。将信息推送到堆栈中：保存指针的值，该指针指向堆栈内的第一个位置作为下一个读取位置; 指针被更新，使得它指向堆栈内的第二位置作为下一个读取位置; 并且将信息写入第二位置处的存储。为了从堆栈弹出信息：响应于指针，从第二位置读取信息作为下一个读取位置; 并且指针被恢复为等于保存的值，使得其指向作为下一个读取位置的第一位置。

3. 发明授权

US09069563B2 Reducing store-hit-loads in an out-of-order processor 有权
标题翻译：减少无序处理器中的存储命中负载
公开(公告)号：US09069563B2
公开(公告)日：2015-06-30
申请号：US13235174
申请日：2011-09-16
申请人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
发明人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3834 , G06F9/3838
摘要： A technique for reducing store-hit-loads in an out-of-order processor includes storing a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry. In response to detecting another SHL pipeline flush for the store address, a current count associated with the SHL entry is updated. In response to the current count associated with the SHL entry reaching a first terminal count, a dependency for the store instruction is created such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes.
摘要翻译：用于减少无序处理器中的存储命中负载的技术包括存储与存储命中加载（SHL）管线冲洗相关联的存储指令的存储地址在SHL条目中。响应于检测存储地址的另一个SHL管道flush，更新与SHL条目相关联的当前计数。响应于与SHL条目相关联的当前计数到达第一终端计数，创建存储指令的依赖关系，使得具有与存储地址重叠的加载地址的较年轻加载指令的执行停止，直到存储指令执行。

4. 发明申请

US20130073833A1 REDUCING STORE-HIT-LOADS IN AN OUT-OF-ORDER PROCESSOR 有权
标题翻译：减少订单处理器中的存储负载
公开(公告)号：US20130073833A1
公开(公告)日：2013-03-21
申请号：US13235174
申请日：2011-09-16
申请人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
发明人： Brian R. Konigsburg , David S. Levitan , Brian R. Mestan , David Mui
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3834 , G06F9/3838
摘要： A technique for reducing store-hit-loads in an out-of-order processor includes storing a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry. In response to detecting another SHL pipeline flush for the store address, a current count associated with the SHL entry is updated. In response to the current count associated with the SHL entry reaching a first terminal count, a dependency for the store instruction is created such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes.
摘要翻译：用于减少无序处理器中的存储命中负载的技术包括存储与存储命中加载（SHL）管线冲洗相关联的存储指令的存储地址在SHL条目中。响应于检测存储地址的另一个SHL管道flush，更新与SHL条目相关联的当前计数。响应于与SHL条目相关联的当前计数到达第一终端计数，创建存储指令的依赖关系，使得具有与存储地址重叠的加载地址的较年轻加载指令的执行停止，直到存储指令执行。

5. 发明申请

US20120005462A1 Hardware Assist for Optimizing Code During Processing 审中-公开
标题翻译：处理过程中优化代码的硬件辅助
公开(公告)号：US20120005462A1
公开(公告)日：2012-01-05
申请号：US12828697
申请日：2010-07-01
申请人： Ronald P. Hall , Brian R. Konigsburg , David S. Levitan , Brian R. Mestan
发明人： Ronald P. Hall , Brian R. Konigsburg , David S. Levitan , Brian R. Mestan
IPC分类号： G06F9/38
CPC分类号： G06F11/3466 , G06F9/3808 , G06F9/3844 , G06F11/348 , G06F2201/88
摘要： A method, data processing system, and computer program product for obtaining information about instructions. Instructions are processed. In response to processing a branch instruction in the instructions, a determination is made as to whether a result from processing the branch instruction follows a prediction of whether a branch is predicted to occur for the branch instruction. In response to the result following the prediction, the branch instruction is added to a current segment in a trace. In response to an absence of the result following the prediction, the branch instruction is added to the current segment in the trace and a first new segment and a second new segment are created. The first new segment includes a first branch instruction reached in the instructions from following the prediction. The second new segment includes a second branch instruction in the instructions reached from not following the prediction.
摘要翻译：一种用于获取关于指令的信息的方法，数据处理系统和计算机程序产品。处理说明。响应于在指令中处理分支指令，确定来自处理分支指令的结果是否遵循预测分支指令是否为分支指令发生的预测。响应于预测结果，分支指令被添加到跟踪中的当前段。响应于预测之后没有结果，分支指令被添加到跟踪中的当前段，并且创建第一新段和第二新段。第一个新的段包括在跟随预测的指令中达到的第一个分支指令。第二个新的段包括从不遵循预测到达的指令中的第二个分支指令。

6. 发明申请

US20080276080A1 METHODS FOR STORING BRANCH INFORMATION IN AN ADDRESS TABLE OF A PROCESSOR 有权
标题翻译：在处理器的地址表中存储分支信息的方法
公开(公告)号：US20080276080A1
公开(公告)日：2008-11-06
申请号：US12171370
申请日：2008-07-11
申请人： Brian R. Konigsburg , David Stephen Levitan , Wolfram M. Sauer , Samuel Jonathan Thomas
发明人： Brian R. Konigsburg , David Stephen Levitan , Wolfram M. Sauer , Samuel Jonathan Thomas
IPC分类号： G06F9/38 , G06F9/44
CPC分类号： G06F9/3806
摘要： Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.
摘要翻译：公开了将分支信息存储在处理器的地址表中的方法。所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。在一些实施例中，地址表还可以适于存储分支信息。

7. 发明授权

US06279105B1 Pipelined two-cycle branch target address cache 失效
标题翻译：流水线两循环分支目标地址缓存
公开(公告)号：US06279105B1
公开(公告)日：2001-08-21
申请号：US09173039
申请日：1998-10-15
申请人： Brian R. Konigsburg , David Stephen Levitan
发明人： Brian R. Konigsburg , David Stephen Levitan
IPC分类号： G06F1300
CPC分类号： G06F9/3806 , G06F9/3836 , G06F9/3861
摘要： In a branch instruction target address cache, an entry associated with a fetched block of instructions includes a target address of a branch instruction residing in the next sequential block of instructions. The entry will include a sequential address associated with the branch instruction and a prediction of whether the target address is taken or not taken.
摘要翻译：在分支指令目标地址高速缓存中，与获取的指令块相关联的条目包括驻留在下一个顺序指令块中的分支指令的目标地址。条目将包括与分支指令相关联的顺序地址以及是否采取目标地址的预测。

8. 发明授权

US06484230B1 Method and system for speculatively processing a load instruction before completion of a preceding synchronization instruction 失效
标题翻译：在完成前一同步指令之前推测加工指令的方法和系统
公开(公告)号：US06484230B1
公开(公告)日：2002-11-19
申请号：US09161640
申请日：1998-09-28
申请人： Brian R. Konigsburg , Alexander Edward Okpisz , Thomas Albert Petersen , Bruce Joseph Ronchetti
发明人： Brian R. Konigsburg , Alexander Edward Okpisz , Thomas Albert Petersen , Bruce Joseph Ronchetti
IPC分类号： G06F1300
CPC分类号： G06F12/0831
摘要： A method and system of facilitating storage accesses within a multiprocessor system subsequent to a synchronization instruction by a local processor consists of determining if data for the storage accesses is cacheable and if there is a “hit” in a cache. If both conditions are met, the storage accesses return the data to the local processor. The storage accesses have an entry on an interrupt table which is used to discard the returned data if a snoop kills the line before the synchronization instruction completes. After the cache returns data, a return data bit is set in the interrupt table. A snoop killing the line sets a snooped bit in the interrupt table. Upon completion of the synchronization instruction, any entries in the interrupt table subsequent to the synchronization instruction that have the return data bit and snooped bit set are flushed. The flush occurs because the data returned to the local processor due to a “cacheable hit” subsequent to the synchronization instruction was out of order with the snoop and the processor must flush the data and go back out to the system bus for the new data.
摘要翻译：在本地处理器的同步指令之后，便于在多处理器系统内存储访问的方法和系统包括确定用于存储访问的数据是否可高速缓存以及高速缓存中是否存在“命中”。如果满足这两个条件，存储访问将数据返回到本地处理器。存储访问在中断表上有一个条目，如果在同步指令完成之前窥探杀死了该行，则该条目用于丢弃返回的数据。缓存返回数据后，在中断表中设置返回数据位。一个窥探杀死线路在中断表中设置一个窥探的位。完成同步指令之后，刷新具有返回数据位和被监听位置位的同步指令之后的中断表中的任何条目。发生冲突是因为由于在同步指令之后的“可缓存命中”返回到本地处理器的数据与snoop不一致，并且处理器必须刷新数据并返回到系统总线以获取新数据。

9. 发明授权

US6021467A Apparatus and method for processing multiple cache misses to a single cache line 失效
标题翻译：用于处理多个高速缓存未命中到单个高速缓存行的装置和方法
公开(公告)号：US6021467A
公开(公告)日：2000-02-01
申请号：US713056
申请日：1996-09-12
申请人： Brian R. Konigsburg , John Stephen Muhich , Larry Edward Thatcher , Steven Wayne White
发明人： Brian R. Konigsburg , John Stephen Muhich , Larry Edward Thatcher , Steven Wayne White
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0859 , G06F12/0897 , Y02B60/1225
摘要： An apparatus and method for processing multiple cache misses to a single cache line in an information handling system which includes a miss queue for storing requests for data not located in a level one cache and a comparator for comparing requests for data stored in the miss queue to determine if there are multiple requests for data located in the same cache line of a level two cache. Each new request for data from the same cache line of the level two cache as an older original request for data in the miss queue is marked as a load hit reload. The requests marked as load hit reloads are then grouped together with the matching original request and forwarded together to the level two cache wherein the original request requests the data from level two cache. The load hit reload requests do not access level two cache but instead bypass access of level two cache by extracting data from the cache line outputted from level two cache for the matching original request. The present invention reduces the number of accesses to the level two cache and allows data requests to be satisfied in parallel versus serially when multiple successive level one cache misses occur.
摘要翻译：一种用于处理信息处理系统中的多个高速缓存未命中到单个高速缓存行的装置和方法，该信息处理系统包括用于存储不在一级高速缓存中的数据的请求的未命中队列，以及比较器，用于将存储在所述未命中队列中的数据的请求与确定是否存在针对二级缓存的同一高速缓存行中的数据的多个请求。来自与二级缓存相同的高速缓存行的数据的新请求作为旧队列中的数据的较早原始请求被标记为加载命中重新加载。标记为加载命中重载的请求随后与匹配的原始请求分组在一起并一起转发到二级缓存，其中原始请求请求来自二级缓存的数据。加载命中重新加载请求不访问二级缓存，而是通过从匹配的原始请求的二级缓存输出的高速缓存行中提取数据来绕过二级缓存的访问。本发明减少对二级高速缓存的访问次数，并且允许当发生多个连续一级高速缓存未命中时并行地对数据请求进行满足。

10. 发明授权

US5805849A Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions 失效
标题翻译：用于使用唯一标识符来维护执行指令之间的年龄关系的数据处理系统和方法
公开(公告)号：US5805849A
公开(公告)日：1998-09-08
申请号：US829592
申请日：1997-03-31
申请人： Paul Joseph Jordan , Brian R. Konigsburg , Hung Qui Le , Steven Wayne White
发明人： Paul Joseph Jordan , Brian R. Konigsburg , Hung Qui Le , Steven Wayne White
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3857
摘要： A data processor assigns a unique identifier to each instruction. As there are a finite number of unique identifiers, the identifiers are reused during execution of a program within the data processing system. To maintain an age relationship between instructions executing in the pipeline processor, a methodology is developed to ensure that reused identifiers are properly designated as being younger than their older but larger in magnitude, counterparts. To resolve this issue, assume that the identifier assigned to each instruction has N bits, and therefore, there are 2.sup.N identifiers to be assigned to instructions in the program. The 2.sup.N identifiers are separated into 2.sup.m banks. In addition to assigning identifiers to each instruction, an identifier assignment logic circuit within the pipeline processor provides a global signal that indicates which bank is a youngest bank from which the identifiers are assigned to a remaining portion of the pipeline processor. The global signal preconditions portions of the two identifiers being compared. Subsequently, a result of this conditioning is concatenated with a remaining portion of a selected identifier. The modification of the upper bits of the identifier maintains a relative age position for the identifiers and their associated instructions in the pipelined processor.
摘要翻译：数据处理器为每个指令分配唯一的标识符。由于存在有限数量的唯一标识符，所以在数据处理系统内的程序执行期间重新使用标识符。为了保持在流水线处理器中执行的指令之间的年龄关系，开发了一种方法，以确保重复使用的标识符被正确地指定为年龄小于较大的，较大的数量。为了解决这个问题，假定分配给每个指令的标识符具有N位，因此，有2N个标识符被分配给程序中的指令。 2N个标识符分成2m个银行。除了为每个指令分配标识符之外，流水线处理器内的标识符分配逻辑电路提供一个全局信号，其指示哪个存储体是最小的存储体，其中标识符从其被分配给流水线处理器的剩余部分。两个标识符的全局信号前提条件部分被比较。随后，这种调理的结果与所选标识符的剩余部分连接。标识符的高位的修改保持流水线处理器中的标识符及其相关联的指令的相对年龄位置。

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