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1. 发明授权

US06654271B2 Method for reading and storing binary memory cells signals and circuit arrangement 有权
标题翻译：读取和存储二进制存储单元信号和电路布置的方法
公开(公告)号：US06654271B2
公开(公告)日：2003-11-25
申请号：US10152950
申请日：2002-05-21
申请人： Karl-Peter Pfefferl , Athanasia Chrysostomides , Dominique Savignac
发明人： Karl-Peter Pfefferl , Athanasia Chrysostomides , Dominique Savignac
IPC分类号： G11C502
CPC分类号： G11C7/18 , G11C7/10 , G11C2207/002
摘要： The invention features a method for reading and storing a binary memory cell signal where a signal transit time of the binary memory cell signal between one memory cell and an output terminal is reduced. The method includes applying a binary memory cell signal to a bit line pair; switching through the binary memory cell signal from the bit line pair to a local data line pair via a sense amplifier; switching through the amplified binary memory cell signal by a main data switching unit from the local data line to a main data line pair; and outputting the amplified, transferred binary memory cell signal via the first main data line and the second main data line pairs.
摘要翻译：本发明的特征在于一种用于读取和存储二进制存储单元信号的方法，其中一个存储单元和输出端之间的二进制存储单元信号的信号传输时间减少。该方法包括将二进制存储单元信号应用于位线对; 通过读出放大器将来自位线对的二进制存储单元信号切换到本地数据线对; 通过主数据交换单元从本地数据线切换到主数据线对的放大的二进制存储单元信号; 以及经由第一主数据线和第二主数据线对输出经放大的二进制存储单元信号。

2. 发明授权

US06721219B2 Method and circuit arrangement for reading out and for storing binary memory cell signals 失效
标题翻译：用于读出和存储二进制存储单元信号的方法和电路装置
公开(公告)号：US06721219B2
公开(公告)日：2004-04-13
申请号：US10150340
申请日：2002-05-17
申请人： Athanasia Chrysostomides , Sabine Kling , Peter Pfefferl , Dominique Savignac , Helmut Schneider
发明人： Athanasia Chrysostomides , Sabine Kling , Peter Pfefferl , Dominique Savignac , Helmut Schneider
IPC分类号： G11C700
CPC分类号： G11C7/065 , G11C2207/002
摘要： The invention provides a method in which a binary memory cell signal from a; least one memory cell is applied to at least one bit line pair (201t, 201b), the binary memory cell signal from the memory tell is switched through via the bit line pair (201t, 201b) to at least one sense amplifier (202), a binary output signal of the sense amplifier (202) is switched through to a local data line pair (205) as a binary intermediate signal, the binary intermediate signal on the local data line pair (205) is switched through to at least one main data line pair (208) by means of a main data line switching transistor pair (209) in a manner dependent on a row control signal fed via a row control line (210), the main data line switching transistor pair (209) being arranged in the through-plating regions formed between the memory cell arrays.
摘要翻译：本发明提供一种方法，其中来自a的二进制存储单元信号，至少一个存储单元被施加到至少一个位线对（201t，201b），来自存储器的二进制存储器单元信号经由位线对（201t，201b）被切换到至少一个读出放大器（202）将读出放大器（202）的二进制输出信号作为二进制中间信号切换到本地数据线对（205），将本地数据线对（205）上的二进制中间信号切换到至少一个主数据线开关晶体管对（209）以主数据线切换晶体管对（209）的方式依赖于通过行控制线（210）馈送的行控制信号，主数据线开关晶体管对（209）布置在形成在存储单元阵列之间的贯通电镀区域中。

3. 发明授权

US06441469B1 Semiconductor memory configuration with dummy components on continuous diffusion regions 有权
标题翻译：具有连续扩散区域上的虚拟部件的半导体存储器配置
公开(公告)号：US06441469B1
公开(公告)日：2002-08-27
申请号：US09511812
申请日：2000-02-24
申请人： Athanasia Chrysostomides , Robert Feurle , Dominique Savignac , Helmut Schneider
发明人： Athanasia Chrysostomides , Robert Feurle , Dominique Savignac , Helmut Schneider
IPC分类号： H01L23552
CPC分类号： H01L27/10897
摘要： The semiconductor memory configuration has at least two memory cell arrays. The open area between the strips of the sense-amp transistors in the two memory cell arrays contains dummy transistors. This avoids proximity effects at the edges of the sense-amp transistors adjoining the open area. The sense-amp transistors and the dummy transistors are arranged in a common, continuous diffusion region.
摘要翻译：半导体存储器配置具有至少两个存储单元阵列。两个存储单元阵列中的读出放大器晶体管的条带之间的开放区域包含虚拟晶体管。这避免了邻近开放区域的感测放大晶体管的边缘处的邻近效应。读出放大器晶体管和虚拟晶体管布置在共同的连续扩散区域中。

4. 发明授权

US06560134B2 Memory configuration with a central connection area 有权
公开(公告)号：US06560134B2
公开(公告)日：2003-05-06
申请号：US10014776
申请日：2001-11-07
申请人： Martin Brox , Karl-Peter Pfefferl , Helmut Schneider , Robert Kaiser , Dominique Savignac
发明人： Martin Brox , Karl-Peter Pfefferl , Helmut Schneider , Robert Kaiser , Dominique Savignac
IPC分类号： G11C502
CPC分类号： G11C5/025 , H01L23/50 , H01L24/02 , H01L27/10805 , H01L2924/01004 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082
摘要： A memory configuration includes a central connection area. The central connection area is surrounded annularly by cell arrays having memory cells. The memory configuration has compact external dimensions and is suitable, in particular, for a side ratio of 2:1. All the peripheral circuits are preferably disposed in the central connection area. As a result, the propagation time differences between the peripheral circuits and the various cell arrays are relatively small.

5. 发明授权

US08293431B2 Lithographic mask and method of forming a lithographic mask 有权
标题翻译：平版印刷掩模和形成光刻掩模的方法
公开(公告)号：US08293431B2
公开(公告)日：2012-10-23
申请号：US12761876
申请日：2010-04-16
申请人： Haiko Rolff , Carla Byloos , Christoph Noelscher , Nicolo Morgana , Roderick Koehle , Molela Moukara , Ralf Neubauer , Rainer Pforr , Dominique Savignac
发明人： Haiko Rolff , Carla Byloos , Christoph Noelscher , Nicolo Morgana , Roderick Koehle , Molela Moukara , Ralf Neubauer , Rainer Pforr , Dominique Savignac
IPC分类号： G03F1/40
CPC分类号： G03F1/40 , G03F1/26 , G03F1/30 , G03F1/32
摘要： A lithographic mask comprises a first layer including grooves, a second layer including regions, sections and a groove-like structure that encloses the sections. The first and second layers are formed so as to reduce electrical potential differences within the second layer. A method of forming a lithographic mask includes forming first and second layers to dispose the second layer over the first layer, patterning the second layer to comprise sections, a region, and a groove-like structure enclosing the sections, and forming grooves in the first layer at portions not covered by the second layer. The first and second layers are formed to reduce potential differences within the second layers during the step of forming the grooves in the first layer.
摘要翻译：平版印刷掩模包括包括凹槽的第一层，包含区域的第二层和包围区段的凹槽状结构。形成第一层和第二层以便减小第二层内的电位差。形成光刻掩模的方法包括形成第一层和第二层以将第二层设置在第一层上，将第二层图案化以包括封闭这些区段的区段，区域和沟槽状结构，以及在第一层中形成凹槽层在未被第二层覆盖的部分。形成第一层和第二层，以在形成第一层中的槽的步骤期间减小第二层内的电位差。

6. 发明授权

US07796446B2 Memory dies for flexible use and method for configuring memory dies 有权
标题翻译：用于灵活使用的存储器模块和用于配置存储器管芯的方法
公开(公告)号：US07796446B2
公开(公告)日：2010-09-14
申请号：US12234312
申请日：2008-09-19
申请人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
发明人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
IPC分类号： G11C7/10
CPC分类号： G11C7/1048 , G11C7/1006 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C29/70 , H01L2224/16145
摘要： A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.
摘要翻译：公开了包括存储器阵列，存储器阵列数据终端和包括第一子总线和第二子总线的数据总线的存储器管芯。还公开了布置在存储器阵列数据终端和第一子总线之间的第一双向缓冲器和布置在存储器阵列数据终端和第二副总线之间的第二双向缓冲器。第一和第二双向缓冲器一次适于将第一子总线或第二子总线耦合到存储器阵列数据终端。

7. 发明授权

US07698470B2 Integrated circuit, chip stack and data processing system 失效
标题翻译：集成电路，芯片堆栈和数据处理系统
公开(公告)号：US07698470B2
公开(公告)日：2010-04-13
申请号：US11834617
申请日：2007-08-06
申请人： Hermann Ruckerbauer , Dominique Savignac
发明人： Hermann Ruckerbauer , Dominique Savignac
IPC分类号： G06F3/00 , H03K19/173 , H01L25/00
CPC分类号： G11C5/04 , G11C5/02 , G11C7/10 , G11C29/1201 , G11C2029/0407 , H01L2224/16145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73257 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit includes a first connection and a memory circuit. The integrated circuit is switchable between a master mode of operation, in which a buffer between the first connection and the memory circuit is activated, and a slave mode of operation, in which the buffer between the first connection and the memory circuit is deactivated.
摘要翻译：集成电路包括第一连接和存储电路。集成电路可以在其中第一连接和存储器电路之间的缓冲器被激活的主操作模式和从动操作模式之间切换，其中第一连接和存储器电路之间的缓冲器被停用。

8. 发明申请

US20090122628A1 DEVICE WITH PRECHARGE/HOMOGENIZE CIRCUIT 有权
标题翻译：具有预充电/均质电路的器件
公开(公告)号：US20090122628A1
公开(公告)日：2009-05-14
申请号：US12122273
申请日：2008-05-16
申请人： Dominique Savignac , Helmut Schneider
发明人： Dominique Savignac , Helmut Schneider
IPC分类号： G11C7/00
CPC分类号： H01L27/10897 , G11C11/4085 , G11C11/4094 , H01L27/0207 , H01L27/105
摘要： A device with a precharge/homogenize circuit. One embodiment provides at least one switching element is acting as a homogenizer, and at least one switching element is acting as a precharger. The diffusion region of the switching element acting as a homogenizer is separated from the diffusion region of the switching element acting as a precharger.
摘要翻译：具有预充电/均质电路的器件。一个实施例提供至少一个开关元件用作均化器，并且至少一个开关元件充当预充电器。作为均化器的开关元件的扩散区域与作为预充电器的开关元件的扩散区域分离。

9. 发明申请

US20080217655A1 INTEGRATED CIRCUIT WITH BURIED CONTROL LINE STRUCTURES 失效
标题翻译：集成电路与布线控制线结构
公开(公告)号：US20080217655A1
公开(公告)日：2008-09-11
申请号：US12028474
申请日：2008-02-08
申请人： Dirk Baumann , Dominique Savignac , Till Schloesser , Helmut Schneider
发明人： Dirk Baumann , Dominique Savignac , Till Schloesser , Helmut Schneider
IPC分类号： H01L29/76
CPC分类号： H01L27/10891
摘要： An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines.
摘要翻译：具有埋地控制线结构的集成电路。在一个实施例中，控制线被细分为多个部分，其中不存在开关晶体管的区域沿着控制线间隔设置。至少在没有开关晶体管的区域的子集中提供用于将控制电位馈送到控制线的部分中的连接。隔离线通过相对于控制线横向运行的互连而彼此连接。

10. 发明申请

US20070033487A1 Semiconductor memory device and method of operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20070033487A1
公开(公告)日：2007-02-08
申请号：US11182063
申请日：2005-07-15
申请人： Hermann Ruckerbauer , Dominique Savignac
发明人： Hermann Ruckerbauer , Dominique Savignac
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1052 , G11C29/42 , G11C2207/104
摘要： A semiconductor memory device including semiconductor memory cells with at least one memory cell capable of either acting as a storage device for ECC information or of acting as a redundant memory cell is provided. The semiconductor memory device further includes a signal control device for signaling if the at least one memory cell is to be used either as a storage device or as a redundant memory cell. A method of operating a semiconductor memory device is also provided including the steps of registering a status of a signal device and, depending on the status of the signal device, operating the at least one memory cell either as a storing device for ECC information or as a redundant memory cell.
摘要翻译：提供一种半导体存储器件，其包括具有至少一个存储单元的半导体存储单元，所述至少一个存储单元可以充当用于ECC信息的存储器件或用作冗余存储器单元。半导体存储器件还包括信号控制装置，用于发信号通知至少一个存储单元是作为存储装置还是用作冗余存储单元。还提供了一种操作半导体存储器件的方法，包括以下步骤：注册信号器件的状态，并且根据信号器件的状态，操作至少一个存储器单元作为ECC信息的存储设备或者作为冗余存储单元。

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