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1. 发明授权

US06560134B2 Memory configuration with a central connection area 有权
公开(公告)号：US06560134B2
公开(公告)日：2003-05-06
申请号：US10014776
申请日：2001-11-07
申请人： Martin Brox , Karl-Peter Pfefferl , Helmut Schneider , Robert Kaiser , Dominique Savignac
发明人： Martin Brox , Karl-Peter Pfefferl , Helmut Schneider , Robert Kaiser , Dominique Savignac
IPC分类号： G11C502
CPC分类号： G11C5/025 , H01L23/50 , H01L24/02 , H01L27/10805 , H01L2924/01004 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082
摘要： A memory configuration includes a central connection area. The central connection area is surrounded annularly by cell arrays having memory cells. The memory configuration has compact external dimensions and is suitable, in particular, for a side ratio of 2:1. All the peripheral circuits are preferably disposed in the central connection area. As a result, the propagation time differences between the peripheral circuits and the various cell arrays are relatively small.

2. 发明授权

US06310793B1 Segmented word line architecture for dividing up a word line into a plurality of banks for cell arrays having long bit lines 有权
标题翻译：用于将字线划分成具有长位线的单元阵列的多个存储体的分段字线架构
公开(公告)号：US06310793B1
公开(公告)日：2001-10-30
申请号：US09663583
申请日：2000-09-18
申请人： Martin Brox , Karl-Peter Pfefferl
发明人： Martin Brox , Karl-Peter Pfefferl
IPC分类号： G11C502
CPC分类号： G11C8/12 , G11C8/14
摘要： The segmented word line architecture has two master word lines, to which sub-word lines are alternately allocated. Two memory banks can thus be alternately assigned to the sub-word lines.
摘要翻译：分段字线架构具有两条主字线，子字线被交替分配。因此，可以将两个存储体交替地分配给子字线。

3. 发明授权

US06295236B1 Semiconductor memory of the random access type with a bus system organized in two planes 有权
标题翻译：具有总线系统的随机存取类型的半导体存储器组织在两个平面中
公开(公告)号：US06295236B1
公开(公告)日：2001-09-25
申请号：US09553128
申请日：2000-04-19
申请人： Martin Brox , Karl-Peter Pfefferl
发明人： Martin Brox , Karl-Peter Pfefferl
IPC分类号： G11C700
CPC分类号： G11C29/70
摘要： The semiconductor memory of the random access type has data lines, which can be connected to the local data lines in the memory cell array. The data lines are combined in groups and at least one group or individual data lines of the groups are formed by redundant data lines. Input/output lines lead from the memory in groups. A bus system organized in two planes is provided. The first plane is provided with bus lines which can be connected to all of the input/output lines, on the one hand, and to all of the data lines, on the other hand. The second plane has a plurality of individual partial buses, whose bus lines can be connected to in each case all of the data lines of at least two groups of data lines, on the one hand, and to all of the input/output lines of in each case one group, on the other hand.
摘要翻译：随机存取类型的半导体存储器具有可连接到存储单元阵列中的本地数据线的数据线。数据线被组合成组，且组中的至少一个组或各个数据线由冗余数据线形成。输入/输出线从组中的内存引出。提供组织在两个飞机上的总线系统。另一方面，第一平面设置有可以连接到所有输入/输出线路以及所有数据线路的总线。第二平面具有多个单独的部分总线，其总线可以在每种情况下连接至少两组数据线的所有数据线，一方面连接到所有输入/输出线另一方面，在每种情况下都是一组。

4. 发明申请

US20050052916A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20050052916A1
公开(公告)日：2005-03-10
申请号：US10878676
申请日：2004-06-29
申请人： Martin Brox , Helmut Schneider
发明人： Martin Brox , Helmut Schneider
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C11/40615 , G11C2211/4067
摘要： The invention relates to semiconductor memories, and in particular, to DRAMs with a memory subunit including a memory cell in which a data value is stored and which is adapted to be connected with a bit line to which a complementary bit line is assigned, and a precharge/equalize circuit assigned to the memory cell, the precharge/equalize circuit serving to charge, prior to the reading out of the memory cell, the bit line and the complementary bit line in the region of the memory cell to the same voltage level, and being switched off during the reading out of the memory cell. The semiconductor memory in addition has a control circuit connected with the precharge/equalize circuit for switching on and off the precharge/equalize circuit.
摘要翻译：本发明涉及半导体存储器，特别涉及具有存储器子单元的DRAM，其中存储器子单元包括其中存储数据值的存储单元，并且适用于与分配有互补位线的位线连接，分配给存储单元的预充电/均衡电路，预充电/均衡电路用于在存储单元的区域读出存储单元之前将位线和互补位线读取到相同的电压电平，并且在读出存储器单元期间被关闭。此外，半导体存储器具有与预充电/均衡电路连接的控制电路，用于接通和关断预充电/均衡电路。

5. 发明申请

US20060087896A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20060087896A1
公开(公告)日：2006-04-27
申请号：US10974019
申请日：2004-10-27
申请人： Martin Brox , Russell Houghton , Helmut Schneider , Sabine Kieser
发明人： Martin Brox , Russell Houghton , Helmut Schneider , Sabine Kieser
IPC分类号： G11C16/04
CPC分类号： G11C11/4076 , G11C7/22 , G11C11/4096 , G11C2207/002
摘要： The invention relates to semiconductor memories and in particular to DRAMs. A semiconductor memory is provided comprising at least one memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal, further comprising a tri-state driver device for driving the control signal. Further, a method for operating a memory is provided, the memory comprising a memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal, the method comprising the steps: driving the control signal at a first voltage level when a read operation is to be performed; and driving the control signal at a second voltage level different from the first voltage level when a write operation is to be performed. Advantageously, the first voltage level used for the read operation is lower than the second voltage level used for the write operation.
摘要翻译：本发明涉及半导体存储器，特别涉及DRAM。提供一种半导体存储器，其包括至少一个适于存储数据值的存储单元，并且适于通过由控制信号控制的开关装置连接到数据线，还包括用于驱动控制信号的三态驱动器装置。此外，提供了一种用于操作存储器的方法，所述存储器包括适于存储数据值的存储单元，并且适于通过由控制信号控制的开关装置连接到数据线，所述方法包括以下步骤：驱动当要执行读取操作时处于第一电压电平的控制信号; 以及当要执行写入操作时，以与所述第一电压电平不同的第二电压电平驱动所述控制信号。有利地，用于读取操作的第一电压电平低于用于写入操作的第二电压电平。

6. 发明授权

US6160747A Configuration for crosstalk attenuation in word lines of DRAM circuits 有权
标题翻译： DRAM电路字线串扰衰减配置
公开(公告)号：US6160747A
公开(公告)日：2000-12-12
申请号：US322718
申请日：1999-05-28
申请人： Martin Brox , Helmut Schneider , Thomas Vogelsang , Michael Killian
发明人： Martin Brox , Helmut Schneider , Thomas Vogelsang , Michael Killian
IPC分类号： G11C8/08 , G11C11/408 , G11C7/00
CPC分类号： G11C11/4085 , G11C8/08
摘要： A configuration for crosstalk attenuation in substantially mutually parallel word lines of DRAM circuits, includes a decoder provided at a first end of a word line, and a holding transistor. A pull-down device is provided as a "noise killer" at a second end of the word line, which opposite the first end. The pull-down device pulls down the potential of the word line in a standby and hold mode in the event of an active adjacent word line.
摘要翻译：在DRAM电路的基本相互平行的字线中的串扰衰减的配置包括设置在字线的第一端的解码器和保持晶体管。在与第一端相对的字线的第二端处提供下拉装置作为“噪声抑制器”。在有效的相邻字线的情况下，下拉装置在待机和保持模式下拉下字线的电位。

7. 发明授权

US07203102B2 Semiconductor memory having tri-state driver device 有权
标题翻译：具有三态驱动器件的半导体存储器
公开(公告)号：US07203102B2
公开(公告)日：2007-04-10
申请号：US10974019
申请日：2004-10-27
申请人： Martin Brox , Russell Houghton , Helmut Schneider , Sabine Kieser
发明人： Martin Brox , Russell Houghton , Helmut Schneider , Sabine Kieser
IPC分类号： G11C7/10
CPC分类号： G11C11/4076 , G11C7/22 , G11C11/4096 , G11C2207/002
摘要： A semiconductor memory having at least one memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal. The invention also relates to a tri-state driver device for driving the control signal. Further, there is a method for operating a memory, in which the memory has a memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal.
摘要翻译：一种半导体存储器，具有适于存储数据值的至少一个存储单元，并且适于通过由控制信号控制的开关装置连接到数据线。本发明还涉及用于驱动控制信号的三态驱动器装置。此外，存在用于操作存储器的方法，其中存储器具有适于存储数据值的存储单元，并且适于通过由控制信号控制的开关装置连接到数据线。

8. 发明授权

US07046564B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07046564B2
公开(公告)日：2006-05-16
申请号：US10878676
申请日：2004-06-29
申请人： Martin Brox , Helmut Schneider
发明人： Martin Brox , Helmut Schneider
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C11/40615 , G11C2211/4067
摘要： The invention relates to semiconductor memories, and in particular, to DRAMs with a memory subunit including a memory cell in which a data value is stored and which is adapted to be connected with a bit line to which a complementary bit line is assigned, and a precharge/equalize circuit assigned to the memory cell, the precharge/equalize circuit serving to charge, prior to the reading out of the memory cell, the bit line and the complementary bit line in the region of the memory cell to the same voltage level, and being switched off during the reading out of the memory cell. The semiconductor memory in addition has a control circuit connected with the precharge/equalize circuit for switching on and off the precharge/equalize circuit.
摘要翻译：本发明涉及半导体存储器，特别涉及具有存储器子单元的DRAM，其中存储器子单元包括其中存储数据值的存储单元，并且适用于与分配有互补位线的位线连接，分配给存储单元的预充电/均衡电路，预充电/均衡电路用于在存储单元的区域读出存储单元之前将位线和互补位线读取到相同的电压电平，并且在读出存储器单元期间被关闭。此外，半导体存储器具有与预充电/均衡电路连接的控制电路，用于接通和关断预充电/均衡电路。

9. 发明授权

US07336552B2 Sense amplifier connecting/disconnecting circuit arrangement and method for operating such a circuit arrangement 有权
标题翻译：感应放大器连接/断开电路布置和操作这种电路装置的方法
公开(公告)号：US07336552B2
公开(公告)日：2008-02-26
申请号：US10927497
申请日：2004-08-27
申请人： Martin Brox , Helmut Schneider
发明人： Martin Brox , Helmut Schneider
IPC分类号： G11C7/12
CPC分类号： G11C11/4091 , G11C7/06 , G11C2207/005
摘要： An apparatus and method for operating a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting/disconnecting a sense amplifier to/from a bit line of a first cell field region, and for connecting/disconnecting the sense amplifier to/from from a bit line of a second cell field region, as a function of the state of control signals applied at control lines. Driver devices drive the control signal. Additional switches change the state of the control signals.
摘要翻译：一种用于操作感测放大器连接/断开电路装置的装置和方法，特别是用于半导体存储器件，包括用于将读出放大器连接到/从第一单元区域的位线连接/断开读取放大器的开关装置，以及用于连接根据在控制线处施加的控制信号的状态，将读出放大器与第二单元区域的位线断开/断开。驱动器驱动控制信号。附加开关改变控制信号的状态。

10. 发明申请

US20050117435A1 Sense amplifier connecting/disconnecting circuit arrangement, and method for operating such a circuit arrangement 有权
标题翻译：感测放大器连接/断开电路装置，以及操作这种电路装置的方法
公开(公告)号：US20050117435A1
公开(公告)日：2005-06-02
申请号：US10927497
申请日：2004-08-27
申请人： Martin Brox , Helmut Schneider
发明人： Martin Brox , Helmut Schneider
IPC分类号： G11C7/06 , G11C11/4091 , G11C7/00
CPC分类号： G11C11/4091 , G11C7/06 , G11C2207/005
摘要： The invention relates to a method for operating a sense amplifier connecting/disconnecting circuit arrangement, and to a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting a sense amplifier device to a bit line or to a cell field region, respectively, and for disconnecting the sense amplifier device from the bit line or from the cell field region, respectively, as a function of the state of a control signal applied at a control line; a driver device for driving the control signal, wherein an additional device, in particular an additional switch is provided, by means of which a change of state of the control signal applied at the control line can be effected.
摘要翻译：本发明涉及一种用于操作读出放大器连接/断开电路装置的方法，以及一种用于读出放大器连接/断开电路装置的方法，特别是涉及一种半导体存储器件，包括用于将读出放大器器件连接到位线或者分别连接到单元场区域，并且用于分别根据在控制线处施加的控制信号的状态来将读出放大器装置分别从位线或单元场区域断开; 用于驱动控制信号的驱动器装置，其中提供附加装置，特别是附加开关，通过该装置可以实现在控制线处施加的控制信号的状态改变。

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