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1. 发明申请

US20080217655A1 INTEGRATED CIRCUIT WITH BURIED CONTROL LINE STRUCTURES 失效
标题翻译：集成电路与布线控制线结构
公开(公告)号：US20080217655A1
公开(公告)日：2008-09-11
申请号：US12028474
申请日：2008-02-08
申请人： Dirk Baumann , Dominique Savignac , Till Schloesser , Helmut Schneider
发明人： Dirk Baumann , Dominique Savignac , Till Schloesser , Helmut Schneider
IPC分类号： H01L29/76
CPC分类号： H01L27/10891
摘要： An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines.
摘要翻译：具有埋地控制线结构的集成电路。在一个实施例中，控制线被细分为多个部分，其中不存在开关晶体管的区域沿着控制线间隔设置。至少在没有开关晶体管的区域的子集中提供用于将控制电位馈送到控制线的部分中的连接。隔离线通过相对于控制线横向运行的互连而彼此连接。

2. 发明授权

US07729154B2 Integrated circuit with buried control line structures 失效
标题翻译：具有埋地控制线结构的集成电路
公开(公告)号：US07729154B2
公开(公告)日：2010-06-01
申请号：US12028474
申请日：2008-02-08
申请人： Dirk Baumann , Dominique Savignac , Till Schloesser , Helmut Schneider
发明人： Dirk Baumann , Dominique Savignac , Till Schloesser , Helmut Schneider
IPC分类号： G11C5/06
CPC分类号： H01L27/10891
摘要： An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines.
摘要翻译：具有埋地控制线结构的集成电路。在一个实施例中，控制线被细分为多个部分，其中不存在开关晶体管的区域沿着控制线间隔设置。至少在没有开关晶体管的区域的子集中提供用于将控制电位馈送到控制线的部分中的连接。隔离线通过相对于控制线横向运行的互连而彼此连接。

3. 发明申请

US20090122628A1 DEVICE WITH PRECHARGE/HOMOGENIZE CIRCUIT 有权
标题翻译：具有预充电/均质电路的器件
公开(公告)号：US20090122628A1
公开(公告)日：2009-05-14
申请号：US12122273
申请日：2008-05-16
申请人： Dominique Savignac , Helmut Schneider
发明人： Dominique Savignac , Helmut Schneider
IPC分类号： G11C7/00
CPC分类号： H01L27/10897 , G11C11/4085 , G11C11/4094 , H01L27/0207 , H01L27/105
摘要： A device with a precharge/homogenize circuit. One embodiment provides at least one switching element is acting as a homogenizer, and at least one switching element is acting as a precharger. The diffusion region of the switching element acting as a homogenizer is separated from the diffusion region of the switching element acting as a precharger.
摘要翻译：具有预充电/均质电路的器件。一个实施例提供至少一个开关元件用作均化器，并且至少一个开关元件充当预充电器。作为均化器的开关元件的扩散区域与作为预充电器的开关元件的扩散区域分离。

4. 发明授权

US06310399B1 Semiconductor memory configuration with a bit-line twist 有权
标题翻译：半导体存储器配置有位线扭曲
公开(公告)号：US06310399B1
公开(公告)日：2001-10-30
申请号：US09514268
申请日：2000-02-28
申请人： Robert Feurle , Sabine Mandel , Dominique Savignac , Helmut Schneider
发明人： Robert Feurle , Sabine Mandel , Dominique Savignac , Helmut Schneider
IPC分类号： H01L2348
CPC分类号： H01L27/10885 , H01L23/5225 , H01L27/10891 , H01L27/10897 , H01L2924/0002 , Y10S257/907 , H01L2924/00
摘要： A semiconductor memory configuration includes bit lines in a bit-line plane, a further plane different from the bit-line plane, word lines, and a memory cell area adjacent the bit-line plane, some of the bit lines having a twist running alongside others of the bit lines being untwisted, pairs of the some of the bit lines with a twist each respectively defining a twist bit-line pair, the twist bit-line pair having contacts for crossing one bit line of the twist bit-line pair over another bit line of the twist bit-line pair and over the memory-cell area through the further plane, the untwisted others of the bit lines having dummy contacts leading from the bit-line plane to the further plane. The dummy contacts lead to the word-line plane to give the word lines a homogeneous environment. The further plane can be a word-line plane including the word lines. The bit lines in the twist-free area can be approximately from 150 nm to 250 nm wide, preferably 200 nm. The twist area can only include the twist of the bit lines. The bit lines in the twist area can be approximately from 250 nm to 350 nm wide, preferably, 330 nm wide. The bit lines can have spacing from 150 to 180 nm wide. The bit lines, the word lines, the contacts, and the dummy contacts can be made from copper or aluminum.
摘要翻译：半导体存储器配置包括位线平面中的位线，不同于位线平面的另一个平面，字线和与位线平面相邻的存储单元区域，一些位线沿着一条扭转位线中的其他位线被解捻，一些位线的对成对分别限定扭转位线对，扭转位线对具有用于使扭转位线对的一个位线交叉的触点扭转位线对的另一个位线和通过另一个平面的存储单元区域之后，未扭绞的其它位线具有从位线平面引导到另一个平面的虚拟触点。虚拟触点导致字线平面，使字线成为均匀的环境。另外的平面可以是包括字线的字线平面。无捻区域中的位线可以约为150nm至250nm宽，优选为200nm。扭曲区域只能包括位线的扭曲。扭转区域中的位线可以约为250nm至350nm宽，优选为330nm宽。位线可以具有150至180nm宽的间距。位线，字线，触点和虚拟触点可以由铜或铝制成。

5. 发明授权

US06426899B1 Integrated memory with a buffer circuit 有权
标题翻译：具有缓冲电路的集成存储器
公开(公告)号：US06426899B1
公开(公告)日：2002-07-30
申请号：US09594911
申请日：2000-06-15
申请人： Dominique Savignac , Robert Feurle , Helmut Schneider
发明人： Dominique Savignac , Robert Feurle , Helmut Schneider
IPC分类号： G11C700
CPC分类号： G11C11/4074 , G11C5/141 , H02J9/061
摘要： An integrated memory includes two potential nodes at which a supply voltage is present. Memory cells each have a selection transistor and a storage capacitor. At least one series circuit is disposed between the two potential nodes. The series circuits each have at least one buffer capacitor and one associated transistor. The associated transistor effects current limiting in the event of a defect in the at least one buffer capacitor. Each of the buffer capacitor and associated transistor have a mutual configuration and dimensions like the selection transistor and storage capacitor of one of the memory cells and have only an electrical connection differing from the selection transistor and storage capacitor.
摘要翻译：集成存储器包括存在电源电压的两个潜在节点。存储单元各自具有选择晶体管和存储电容器。在两个电位节点之间设置至少一个串联电路。串联电路各自具有至少一个缓冲电容器和一个相关联的晶体管。相关的晶体管在至少一个缓冲电容器的缺陷的情况下影响电流限制。缓冲电容器和相关晶体管中的每一个具有与存储单元之一的选择晶体管和存储电容器相互的配置和尺寸，并且仅具有与选择晶体管和存储电容器不同的电连接。

6. 发明授权

US06294841B1 Integrated semiconductor circuit having dummy structures 有权
标题翻译：具有虚拟结构的集成半导体电路
公开(公告)号：US06294841B1
公开(公告)日：2001-09-25
申请号：US09327699
申请日：1999-06-08
申请人： Dominique Savignac , Robert Feurle , Helmut Schneider
发明人： Dominique Savignac , Robert Feurle , Helmut Schneider
IPC分类号： H01L2348
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： An integrated semiconductor circuit includes dummy structures. A portion of capacitive elements present in the dummy structures is used in order to adapt input/output parameters of pads of the integrated semiconductor circuit to an external line. Metal options, fuses or switches are suitable for the connection. The structure is neutral with respect to surface area.
摘要翻译：集成半导体电路包括虚拟结构。为了使集成半导体电路的焊盘的输入/输出参数适应于外部线路，使用存在于虚拟结构中的电容元件的一部分。金属选件，保险丝或开关适用于连接。该结构相对于表面积是中性的。

7. 发明授权

US07808853B2 Semiconductor memory device and method with a changeable substrate potential 有权
标题翻译：具有可变衬底电位的半导体存储器件和方法
公开(公告)号：US07808853B2
公开(公告)日：2010-10-05
申请号：US12032336
申请日：2008-02-15
申请人： Marc Berthel , Axel Strobel , Dominique Savignac , Helmut Schneider
发明人： Marc Berthel , Axel Strobel , Dominique Savignac , Helmut Schneider
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/4074 , G11C5/146 , G11C7/06 , G11C7/065 , G11C7/08 , G11C8/18 , G11C11/4091
摘要： A semiconductor memory device and method with a changeable substrate potential. One embodiment provides for operating a semiconductor memory device having at least one read or write/sense amplifier. The method includes changing the substrate potential of the read or write/sense amplifier.
摘要翻译：具有可变基板电位的半导体存储器件和方法。一个实施例提供了用于操作具有至少一个读/写/读放大器的半导体存储器件。该方法包括改变读/写/读出放大器的衬底电位。

8. 发明授权

US06560134B2 Memory configuration with a central connection area 有权
公开(公告)号：US06560134B2
公开(公告)日：2003-05-06
申请号：US10014776
申请日：2001-11-07
申请人： Martin Brox , Karl-Peter Pfefferl , Helmut Schneider , Robert Kaiser , Dominique Savignac
发明人： Martin Brox , Karl-Peter Pfefferl , Helmut Schneider , Robert Kaiser , Dominique Savignac
IPC分类号： G11C502
CPC分类号： G11C5/025 , H01L23/50 , H01L24/02 , H01L27/10805 , H01L2924/01004 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082
摘要： A memory configuration includes a central connection area. The central connection area is surrounded annularly by cell arrays having memory cells. The memory configuration has compact external dimensions and is suitable, in particular, for a side ratio of 2:1. All the peripheral circuits are preferably disposed in the central connection area. As a result, the propagation time differences between the peripheral circuits and the various cell arrays are relatively small.

9. 发明授权

US06441469B1 Semiconductor memory configuration with dummy components on continuous diffusion regions 有权
标题翻译：具有连续扩散区域上的虚拟部件的半导体存储器配置
公开(公告)号：US06441469B1
公开(公告)日：2002-08-27
申请号：US09511812
申请日：2000-02-24
申请人： Athanasia Chrysostomides , Robert Feurle , Dominique Savignac , Helmut Schneider
发明人： Athanasia Chrysostomides , Robert Feurle , Dominique Savignac , Helmut Schneider
IPC分类号： H01L23552
CPC分类号： H01L27/10897
摘要： The semiconductor memory configuration has at least two memory cell arrays. The open area between the strips of the sense-amp transistors in the two memory cell arrays contains dummy transistors. This avoids proximity effects at the edges of the sense-amp transistors adjoining the open area. The sense-amp transistors and the dummy transistors are arranged in a common, continuous diffusion region.
摘要翻译：半导体存储器配置具有至少两个存储单元阵列。两个存储单元阵列中的读出放大器晶体管的条带之间的开放区域包含虚拟晶体管。这避免了邻近开放区域的感测放大晶体管的边缘处的邻近效应。读出放大器晶体管和虚拟晶体管布置在共同的连续扩散区域中。

10. 发明授权

US06317378B1 Buffer circuit 有权
标题翻译：缓冲电路
公开(公告)号：US06317378B1
公开(公告)日：2001-11-13
申请号：US09592225
申请日：2000-06-12
申请人： Dominique Savignac , Robert Feurle , Helmut Schneider
发明人： Dominique Savignac , Robert Feurle , Helmut Schneider
IPC分类号： G11C514
CPC分类号： H03K19/017509 , G05F3/247
摘要： A buffer circuit serves for buffering a supply voltage of an integrated circuit. The supply voltage is present between two potential nodes. A series circuit is disposed between the two potential nodes and includes at least two buffer capacitors between which a third potential node is disposed. The third potential node is connected to an additional circuit which influences the potential of the third potential node in such a way that it does not exceed an upper and/or lower limit value when a leakage current occurs through one of the capacitors. The advantage of the buffer circuit is that when there is a defect in just one of the buffer capacitors, the other capacitor is prevented from being destroyed.
摘要翻译：缓冲电路用于缓冲集成电路的电源电压。电源电压存在于两个电位节点之间。串联电路设置在两个电位节点之间，并且包括至少两个缓冲电容器，第三电位节点之间设置有缓冲电容器。第三电位节点连接到附加电路，该附加电路以这样的方式影响第三电位节点的电位，使得当通过电容器之一发生漏电流时，其不超过上限值和/或下限值。缓冲电路的优点在于，当仅缓冲电容器中的一个存在缺陷时，防止另一电容器被破坏。

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