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1. 发明申请

US20090039915A1 Integrated Circuit, Chip Stack and Data Processing System 失效
标题翻译：集成电路，芯片堆栈和数据处理系统
公开(公告)号：US20090039915A1
公开(公告)日：2009-02-12
申请号：US11834617
申请日：2007-08-06
申请人： Hermann Ruckerbauer , Dominique Savignac
发明人： Hermann Ruckerbauer , Dominique Savignac
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G11C5/04 , G11C5/02 , G11C7/10 , G11C29/1201 , G11C2029/0407 , H01L2224/16145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73257 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit includes a first connection and a memory circuit. The integrated circuit is switchable between a master mode of operation, in which a buffer between the first connection and the memory circuit is activated, and a slave mode of operation, in which the buffer between the first connection and the memory circuit is deactivated.
摘要翻译：集成电路包括第一连接和存储电路。集成电路可以在其中第一连接和存储器电路之间的缓冲器被激活的主操作模式和从动操作模式之间切换，其中第一连接和存储器电路之间的缓冲器被停用。

2. 发明授权

US07173877B2 Memory system with two clock lines and a memory device 有权
标题翻译：具有两个时钟线和存储器件的存储器系统
公开(公告)号：US07173877B2
公开(公告)日：2007-02-06
申请号：US10955177
申请日：2004-09-30
申请人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Christian Sichert , Dominique Savignac , Peter Gregorius , Paul Wallner
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/063 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.
摘要翻译：本发明涉及一种具有两条时钟线的存储器件的存储器系统。本发明的一个实施例提供了一种存储器系统，其包括至少一个存储器件，用于控制存储器件的操作的存储器控制器，从存储器控制器的写时钟输出延伸到存储器的时钟端口的第一时钟线向存储器件提供时钟信号的第二时钟线，以及从存储器件的时钟端口延伸到存储器控制器的读时钟输入端的第二时钟线，以将施加到存储器件的时钟端口的时钟信号转发回到存储器控制器的读时钟输入。存储器件还可以包括同步电路，其适于从存储器控制器接收时钟信号，并提供与转发的时钟信号同步的输出数据。

3. 发明授权

US07050340B1 Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system 有权
标题翻译：半导体存储器系统和用于在半导体存储器系统中传送写和读数据信号的方法
公开(公告)号：US07050340B1
公开(公告)日：2006-05-23
申请号：US10986767
申请日：2004-11-15
申请人： Hermann Ruckerbauer , Dominique Savignac , Christian Sichert , Peter Gregorius , Paul Wallner
发明人： Hermann Ruckerbauer , Dominique Savignac , Christian Sichert , Peter Gregorius , Paul Wallner
IPC分类号： G11C7/00
CPC分类号： G11C7/1045 , G11C5/04 , G11C7/1018
摘要： A semiconductor memory system for the transfer of write and read data signals among interface circuits includes at least one memory device, a memory controller unit and, optionally, a register unit of a semiconductor memory system, wherein the data signals are each transferred in signal bursts of a specific burst length. The system is characterized in that a number of additional bits extending the burst length are transferred together with at least every nth signal burst.
摘要翻译：用于在接口电路之间传送写入和读取数据信号的半导体存储器系统包括至少一个存储器件，存储器控制器单元和可选地半导体存储器系统的寄存器单元，其中数据信号各自以信号脉冲串具体的突发长度。该系统的特征在于，延伸突发长度的多个附加位与至少每个第n个信号脉冲串一起传送。

4. 发明授权

US07796446B2 Memory dies for flexible use and method for configuring memory dies 有权
标题翻译：用于灵活使用的存储器模块和用于配置存储器管芯的方法
公开(公告)号：US07796446B2
公开(公告)日：2010-09-14
申请号：US12234312
申请日：2008-09-19
申请人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
发明人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
IPC分类号： G11C7/10
CPC分类号： G11C7/1048 , G11C7/1006 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C29/70 , H01L2224/16145
摘要： A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.
摘要翻译：公开了包括存储器阵列，存储器阵列数据终端和包括第一子总线和第二子总线的数据总线的存储器管芯。还公开了布置在存储器阵列数据终端和第一子总线之间的第一双向缓冲器和布置在存储器阵列数据终端和第二副总线之间的第二双向缓冲器。第一和第二双向缓冲器一次适于将第一子总线或第二子总线耦合到存储器阵列数据终端。

5. 发明授权

US07698470B2 Integrated circuit, chip stack and data processing system 失效
标题翻译：集成电路，芯片堆栈和数据处理系统
公开(公告)号：US07698470B2
公开(公告)日：2010-04-13
申请号：US11834617
申请日：2007-08-06
申请人： Hermann Ruckerbauer , Dominique Savignac
发明人： Hermann Ruckerbauer , Dominique Savignac
IPC分类号： G06F3/00 , H03K19/173 , H01L25/00
CPC分类号： G11C5/04 , G11C5/02 , G11C7/10 , G11C29/1201 , G11C2029/0407 , H01L2224/16145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73257 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit includes a first connection and a memory circuit. The integrated circuit is switchable between a master mode of operation, in which a buffer between the first connection and the memory circuit is activated, and a slave mode of operation, in which the buffer between the first connection and the memory circuit is deactivated.
摘要翻译：集成电路包括第一连接和存储电路。集成电路可以在其中第一连接和存储器电路之间的缓冲器被激活的主操作模式和从动操作模式之间切换，其中第一连接和存储器电路之间的缓冲器被停用。

6. 发明申请

US20070033487A1 Semiconductor memory device and method of operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20070033487A1
公开(公告)日：2007-02-08
申请号：US11182063
申请日：2005-07-15
申请人： Hermann Ruckerbauer , Dominique Savignac
发明人： Hermann Ruckerbauer , Dominique Savignac
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1052 , G11C29/42 , G11C2207/104
摘要： A semiconductor memory device including semiconductor memory cells with at least one memory cell capable of either acting as a storage device for ECC information or of acting as a redundant memory cell is provided. The semiconductor memory device further includes a signal control device for signaling if the at least one memory cell is to be used either as a storage device or as a redundant memory cell. A method of operating a semiconductor memory device is also provided including the steps of registering a status of a signal device and, depending on the status of the signal device, operating the at least one memory cell either as a storing device for ECC information or as a redundant memory cell.
摘要翻译：提供一种半导体存储器件，其包括具有至少一个存储单元的半导体存储单元，所述至少一个存储单元可以充当用于ECC信息的存储器件或用作冗余存储器单元。半导体存储器件还包括信号控制装置，用于发信号通知至少一个存储单元是作为存储装置还是用作冗余存储单元。还提供了一种操作半导体存储器件的方法，包括以下步骤：注册信号器件的状态，并且根据信号器件的状态，操作至少一个存储器单元作为ECC信息的存储设备或者作为冗余存储单元。

7. 发明授权

US08547767B2 Chip, multi-chip system in a method for performing a refresh of a memory array 失效
标题翻译：用于执行存储器阵列的刷新的方法中的芯片，多芯片系统
公开(公告)号：US08547767B2
公开(公告)日：2013-10-01
申请号：US12108383
申请日：2008-04-23
申请人： Hermann Ruckerbauer , Dominique Savignac
发明人： Hermann Ruckerbauer , Dominique Savignac
IPC分类号： G11C11/406 , G11C11/4076
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40615
摘要： A chip includes a memory array and a refresh counter. The refresh counter is configured to receive refresh trigger signals. The refresh counter is configured or configurable to initiate a refresh of the memory array only once per i of the received refresh trigger signals where i is a number greater than 1.
摘要翻译：芯片包括存储器阵列和刷新计数器。刷新计数器被配置为接收刷新触发信号。刷新计数器被配置或配置为仅在接收到的刷新触发信号（i是大于1的数量）的情况下才开始刷新存储器阵列一次。

8. 发明申请

US20100074038A1 Memory Dies for Flexible Use and Method for Configuring Memory Dies 有权
标题翻译：用于灵活使用的内存模式和配置内存模块的方法
公开(公告)号：US20100074038A1
公开(公告)日：2010-03-25
申请号：US12234312
申请日：2008-09-19
申请人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
发明人： Hermann Ruckerbauer , Michael Bruennert , Ullrich Menczigar , Christian Mueller , Sitt Tontisirin , Georg Braun , Dominique Savignac
IPC分类号： G11C7/10 , H01L21/66 , H01L23/538
CPC分类号： G11C7/1048 , G11C7/1006 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C29/70 , H01L2224/16145
摘要： A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.
摘要翻译：公开了包括存储器阵列，存储器阵列数据终端和包括第一子总线和第二子总线的数据总线的存储器管芯。还公开了布置在存储器阵列数据终端和第一子总线之间的第一双向缓冲器和布置在存储器阵列数据终端和第二副总线之间的第二双向缓冲器。第一和第二双向缓冲器一次适于将第一子总线或第二子总线耦合到存储器阵列数据终端。

9. 发明授权

US07397684B2 Semiconductor memory array with serial control/address bus 有权
标题翻译：具有串行控制/地址总线的半导体存储器阵列
公开(公告)号：US07397684B2
公开(公告)日：2008-07-08
申请号：US11226447
申请日：2005-09-15
申请人： Hermann Ruckerbauer , Ralf Schledz , Johannes Stecker , Dominique Savignac , Georg Braun
发明人： Hermann Ruckerbauer , Ralf Schledz , Johannes Stecker , Dominique Savignac , Georg Braun
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G06F13/1668
摘要： A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and address signals connected with the memory controller, directly connecting at least one semiconductor memory chip with the memory controller and serially connecting with each other the semiconductor memory chips among each other by 1-point-to-1-point connections.
摘要翻译：一种用于在具有用于存储用户数据的至少一个半导体存储器芯片和用于控制至少一个半导体存储器芯片的一个存储器控制器的数据存储系统中操作的半导体存储器阵列包括至少一个用于控制的单向串行信号线总线以及与存储器控制器连接的地址信号，将至少一个半导体存储器芯片与存储器控制器直接连接，并且通过1点到1点连接彼此串联连接半导体存储器芯片。

10. 发明申请

US20070195505A1 Memory module device 审中-公开
标题翻译：内存模块设备
公开(公告)号：US20070195505A1
公开(公告)日：2007-08-23
申请号：US11357413
申请日：2006-02-21
申请人： Dominique Savignac , Peter Gregorius , Hermann Ruckerbauer , Simon Muff
发明人： Dominique Savignac , Peter Gregorius , Hermann Ruckerbauer , Simon Muff
IPC分类号： H05K7/20
CPC分类号： H05K1/183 , G11C5/02 , G11C5/025 , G11C5/04 , H01L23/552 , H01L24/73 , H01L25/18 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2924/01019 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/16195 , H01L2924/16251 , H01L2924/19107 , H01L2924/3025 , H05K1/181 , H05K2201/10159 , H05K2201/10515 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A memory module device includes a printed circuit board, a plurality of memory modules and a buffer module. Lines are provided in or on the printed circuit board to connect the buffer module to the memory modules. The memory modules are combined at least partially to form memory module stacks.
摘要翻译：存储器模块装置包括印刷电路板，多个存储器模块和缓冲模块。在印刷电路板中或印刷电路板上提供线路，以将缓冲模块连接到存储器模块。存储器模块至少部分地组合以形成存储器模块堆栈。

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