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1. 发明申请

US20140009371A1 ALLOCATING REGISTERS ON A SPATIAL LIGHT MODULATOR 有权
标题翻译：在空调光调制器上分配寄存器
公开(公告)号：US20140009371A1
公开(公告)日：2014-01-09
申请号：US14012292
申请日：2013-08-28
申请人： Karl M. Guttag
发明人： Karl M. Guttag
IPC分类号： G09G5/10
CPC分类号： G09G5/10 , G06F3/147 , G09G3/2014 , G09G3/2022 , G09G3/34 , G09G3/346 , G09G2300/0809 , G09G2300/0857 , G09G2310/0221 , G09G2310/0275
摘要： Described is a device comprising: an array of light modulating elements; and one or more processing elements for controlling each of the light modulating elements, wherein the light modulating elements are arranged in a two-dimensional array, and wherein the one or more processing elements are adapted to skip some bit locations and use other bit locations of bit values when performing multiple bit logical and/or arithmetic operations.
摘要翻译：描述了一种装置，包括：光调制元件阵列; 以及用于控制每个光调制元件的一个或多个处理元件，其中所述光调制元件被布置成二维阵列，并且其中所述一个或多个处理元件适于跳过某些位位置并使用其它位位置执行多位逻辑和/或算术运算时的位值。

2. 发明授权

US07667678B2 Recursive feedback control of light modulating elements 有权
标题翻译：光调制元件的递归反馈控制
公开(公告)号：US07667678B2
公开(公告)日：2010-02-23
申请号：US11382547
申请日：2006-05-10
申请人： Karl M. Guttag
发明人： Karl M. Guttag
IPC分类号： G09G3/36
CPC分类号： G09G5/10 , G06F3/147 , G09G3/2014 , G09G3/2022 , G09G3/34 , G09G3/346 , G09G2300/0809 , G09G2300/0857 , G09G2310/0221 , G09G2310/0275
摘要： In one embodiment, the present invention, one or more light modulating elements are controlled by a method comprising the following steps: controlling at least one pulse width using recursive feedback; and driving an electrode means using the pulse width to thereby control a light modulating element of an array of light modulating elements. In other embodiments, the present invention provides a method and system for determining a pulse wave form for each line of a two-dimensional array of drive bits using a recursive feedback process, wherein each drive bit in the array of drive bits is in an initialized state; and for turning all of the drive bits to an off state to thereby produce a blanking interval between fields for an image, wherein control of each of the pulse wave forms is staggered in time.
摘要翻译：在一个实施例中，本发明通过包括以下步骤的方法控制一个或多个光调制元件：使用递归反馈来控制至少一个脉冲宽度; 并且使用脉冲宽度驱动电极装置，从而控制光调制元件阵列的光调制元件。在其他实施例中，本发明提供一种用于使用递归反馈处理来确定驱动位二维阵列的每行的脉冲波形的方法和系统，其中驱动位阵列中的每个驱动位处于初始化状态州; 并且用于将所有驱动位转到关闭状态，从而在图像的场之间产生消隐间隔，其中每个脉冲波形的控制在时间上交错。

3. 发明授权

US07071908B2 Digital backplane 有权
标题翻译：数字背板
公开(公告)号：US07071908B2
公开(公告)日：2006-07-04
申请号：US10849195
申请日：2004-05-20
申请人： Karl M. Guttag , Alvin Guttag
发明人： Karl M. Guttag , Alvin Guttag
IPC分类号： G09G3/36
CPC分类号： G09G5/10 , G06F3/147 , G09G3/2014 , G09G3/2022 , G09G3/34 , G09G3/346 , G09G2300/0809 , G09G2300/0857 , G09G2310/0221 , G09G2310/0275
摘要： The present invention provides a various methods, systems and devices for controlling light modulating elements and/or spatial light modulators. In some embodiments of the present invention, a recursive feedback method is used to control light modulating elements and/or spatial light modulators.
摘要翻译：本发明提供了用于控制光调制元件和/或空间光调制器的各种方法，系统和装置。在本发明的一些实施例中，使用递归反馈方法来控制光调制元件和/或空间光调制器。

4. 发明授权

US07039795B2 System and method for using a two-stage multiplexing architecture for performing combinations of passing, rearranging, and duplicating operations on data 有权
标题翻译：用于使用两级复用架构来执行对数据的传递，重新排列和复制操作的组合的系统和方法
公开(公告)号：US07039795B2
公开(公告)日：2006-05-02
申请号：US10172221
申请日：2002-06-14
申请人： Keith Balmer , Karl M. Guttag , Amarjit Singh Bhandal
发明人： Keith Balmer , Karl M. Guttag , Amarjit Singh Bhandal
IPC分类号： G06F9/315
CPC分类号： G06F9/30032
摘要： A method for processing data using a multiplexing architecture includes performing a selected one of a plurality of first multiplexer operations on the data and then a selected one of a plurality of second multiplexer operations. The first multiplexer operations include a pass operation and a plurality of bit rearrangement operations. The second multiplexer operations include a pass operation and a plurality of bit duplication operations which duplicates a selected bit or bits to a corresponding block of contiguous bits in the output. A result is then generated that reflects the outputs produced by first and second multiplexers respectively.
摘要翻译：使用复用架构来处理数据的方法包括：对数据执行多个第一复用器操作中的所选择的一个，然后执行多个第二复用器操作中的所选择的一个。第一复用器操作包括通过操作和多个位重排操作。第二多路复用器操作包括将所选择的比特复制到输出中相应的连续比特块的通过操作和多个比特复制操作。然后产生分别反映由第一和第二多路复用器产生的输出的结果。

5. 发明授权

US06829696B1 Data processing system with register store/load utilizing data packing/unpacking 有权
标题翻译：数据处理系统，具有使用数据打包/打包的寄存器存储/负载
公开(公告)号：US06829696B1
公开(公告)日：2004-12-07
申请号：US09687540
申请日：2000-10-13
申请人： Keith Balmer , Karl M. Guttag , Lewis Nardini
发明人： Keith Balmer , Karl M. Guttag , Lewis Nardini
IPC分类号： G06F9312
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/345 , G06F9/3824 , G06F9/3828 , G06F9/3853
摘要： A data processing system (e.g., microprocessor 30) for packing register data while storing it to memory and unpacking data read from memory while loading it into registers using single processor instructions. The system comprises a memory (42) and a central processing unit core (44) with at least one register file (76). The core is responsive to a load instruction (e.g., LDW_BH[U] instruction 184) to retrieve at least one data word from memory and parse the data word over selected parts of at least two data registers in the register file. The core is responsive to a store instruction (e.g., STBH_W instruction 198) to concatenate data from selected parts of at least two data registers into at least one data word and save the data word to memory. The number of data registers is greater than the number of data words parsed into or concatenated from the data registers. Both memory storage space and central processor unit resources are utilized efficiently when working with packed data. A single store or load instruction can perform all of the tasks that used to take several instructions, while at the same time conserving memory space.
摘要翻译：数据处理系统（例如，微处理器30），用于打包寄存器数据，同时将其存储到存储器并且解包从存储器读取的数据，同时使用单个处理器指令将其加载到寄存器中。该系统包括具有至少一个寄存器文件（76）的存储器（42）和中央处理单元核心（44）。核心响应于加载指令（例如LDW_BH [U]指令184））从存储器检索至少一个数据字，并且通过寄存器文件中的至少两个数据寄存器的选定部分解析数据字。核心响应于存储指令（例如，STBH_W指令198）将从至少两个数据寄存器的所选部分的数据连接到至少一个数据字中并将数据字保存到存储器。数据寄存器的数量大于从数据寄存器解析或级联的数据字数。当处理打包数据时，存储器存储空间和中央处理器单元资源都被有效利用。单个存储或加载指令可以执行用于执行多个指令的所有任务，同时节省内存空间。

6. 发明授权

US06754809B1 Data processing apparatus with indirect register file access 有权
标题翻译：具有间接寄存器文件访问的数据处理设备
公开(公告)号：US06754809B1
公开(公告)日：2004-06-22
申请号：US09713442
申请日：2000-11-15
申请人： Karl M. Guttag , David Hoyle , Keith Balmer
发明人： Karl M. Guttag , David Hoyle , Keith Balmer
IPC分类号： G06F934
CPC分类号： G06F9/3012 , G06F9/3004 , G06F9/30098 , G06F9/35 , G06F9/383
摘要： A data processing apparatus which uses a register file to provide a faster alternative to indirect memory addressing. A functional unit is connected to a data register file (76) which comprises a plurality of registers, each of which is accessed by a corresponding register number. The functional unit (e.g., A-unit 78) can execute at least one indirect register access instruction that comprises an operand register number field. Instruction decode circuitry, connected to the register file and the functional unit, is responsive to the indirect register access instruction to recall data stored in an operand register (190) specified by the operand register number in the instruction, identify the recalled data as a register access number, and recall operand data from a data register corresponding to the register access number for use as an operand by the functional unit. Indirect register addressing permits the apparatus to more quickly execute table look up intensive algorithms, such as variable length decoding, than an apparatus employing only indirect memory addressing.
摘要翻译：一种使用寄存器文件来提供间接存储器寻址的更快替代的数据处理装置。功能单元连接到数据寄存器文件（76），数据寄存器文件（76）包括多个寄存器，每个寄存器都由对应的寄存器号码访问。功能单元（例如，A单元78）可以执行包括操作数寄存器号字段的至少一个间接寄存器访问指令。连接到寄存器文件和功能单元的指令解码电路响应于间接寄存器访问指令来调用存储在指令中由操作数寄存器号指定的操作数寄存器（190）中的数据，将调用的数据标识为寄存器访问号码，并且从与寄存器访问号相对应的数据寄存器中调用操作数数据，以用作功能单元的操作数。间接寄存器寻址允许装置比仅使用间接存储器寻址的装置更快速地执行表查找密集型算法，例如可变长度解码。

7. 发明授权

US06314047B1 Low cost alternative to large dual port RAM 有权
标题翻译：低成本替代大型双端口RAM
公开(公告)号：US06314047B1
公开(公告)日：2001-11-06
申请号：US09713560
申请日：2000-11-15
申请人： John Keay , Iain Robertson , Karl M. Guttag , Keith Balmer
发明人： John Keay , Iain Robertson , Karl M. Guttag , Keith Balmer
IPC分类号： G11C800
CPC分类号： G11C11/412 , G11C8/16
摘要： Data transfer between multiple processor nodes and multiple static memory storage nodes is made more efficient using a wrapper of logic surrounding a conventional single port static memory function. The wrapper logic comprises FIFO devices which provide buffering between a given processor node and its associated memory function. The added buffering allows the design to trade allowable added read and write latency for a significant reduction in memory complexity. A single port random access memory structure enclosed within the wrapper provides the functional throughput advantage that only a dual port memory device would otherwise make possible.
摘要翻译：使用围绕常规单端口静态存储器功能的逻辑封装件，使多个处理器节点和多个静态存储器存储节点之间的数据传输变得更有效。封装逻辑包括提供给定处理器节点与其相关联的存储器功能之间的缓冲的FIFO设备。添加的缓冲允许设计交易允许的增加的读和写延迟，显着降低内存复杂性。包装在封装件中的单端口随机存取存储器结构提供了功能吞吐量优点，即只有双端口存储器件将成为可能。

8. 发明授权

US6088280A High-speed memory arranged for operating synchronously with a microprocessor 失效
标题翻译：高速存储器布置成与微处理器同步操作
公开(公告)号：US6088280A
公开(公告)日：2000-07-11
申请号：US413928
申请日：1999-10-07
申请人： Wilbur Christian Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur Christian Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译：同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。同步随机存取存储器件可以制造为动态存储器件或静态存储器件。

9. 发明授权

US5956744A Memory configuration cache with multilevel hierarchy least recently used cache entry replacement 失效
标题翻译：具有多级层次结构的内存配置缓存最近使用的缓存条目替换
公开(公告)号：US5956744A
公开(公告)日：1999-09-21
申请号：US706618
申请日：1996-09-06
申请人： Iain Robertson , Karl M. Guttag , Eric R. Hansen
发明人： Iain Robertson , Karl M. Guttag , Eric R. Hansen
IPC分类号： G06F12/12
CPC分类号： G06F12/123
摘要： A multilevel hierarchical least recently used cache replacement priority in a digital data processing system including plural memories, each memory connected to said system bus for memory access, a memory address generator generating addresses for read access to a corresponding of the memories and a memory cache having a plurality of cache entries, each cache entry including a range of addresses and a predetermined set of cache words. During each memory read the comparator compares the generated address with the address range of each cache entry. If there is a match, then the cache supplies a cache word corresponding to the least significant bits of the generated address from the matching cache entry. If there is no such match, the generated address is supplied to the memories and a set of words is recalled corresponding to the generated address. This set of words replaces a least recently used prior stored memory cache entry having the lowest priority level. The priority level for each cache entry may be recalled from a cache priority level look-up table or entered from an instruction via coding in opcode bits or a priority setting instruction. In an alternative embodiment this technique is used with a memory configuration cache storing memory access parameters for corresponding address ranges enabling adaption to plural memories requiring differing sets of memory access parameters.
摘要翻译：在包括多个存储器的数字数据处理系统中的多级分级最低最近使用的高速缓存替换优先级，连接到所述系统总线的每个存储器用于存储器访问，存储器地址生成器产生用于对对应的存储器进行读访问的地址和具有多个高速缓存条目，每个高速缓存条目包括地址范围和预定的一组高速缓存字。在每个存储器读取期间，比较器将生成的地址与每个高速缓存条目的地址范围进行比较。如果存在匹配，则高速缓存从匹配的高速缓存条目提供对应于生成的地址的最低有效位的缓存字。如果没有这样的匹配，则将生成的地址提供给存储器，并且根据生成的地址来调用一组字。这组文字替代了具有最低优先级的最近最少使用的先前存储的存储器高速缓存条目。每个高速缓存条目的优先级可以从高速缓存优先级查找表调用，或者通过操作码中的编码或优先级设置指令从指令中输入。在替代实施例中，该技术与存储器配置高速缓存一起使用，存储器访问参数用于相应的地址范围，使得能够适应需要不同组的存储器访问参数的多个存储器。

10. 发明授权

US5923340A Process of processing graphics data 失效
标题翻译：处理图形数据的过程
公开(公告)号：US5923340A
公开(公告)日：1999-07-13
申请号：US485540
申请日：1995-06-07
申请人： Karl M. Guttag , Michael D. Asal , Jerry R. Van Aken , Neil Tebbutt , Mark F. Novak
发明人： Karl M. Guttag , Michael D. Asal , Jerry R. Van Aken , Neil Tebbutt , Mark F. Novak
IPC分类号： G06T1/20 , G09G5/393 , G06F12/06
CPC分类号： G06T1/20 , G09G5/393 , G09G2340/10
摘要： The graphics data processor of the present invention offers as a single instruction in its instruction set a draw and advance operation. A first data register stores a set of X and Y coordinates. In a first embodiment, a predetermined color code is stored at the pixel address of a bit mapped display memory indicated by the X and Y coordinates the first data register upon execution of the the draw and advance instruction. The X and Y coordinates stored in the first data register are then advanced by addition of X and Y coordinates stored in a second data register. A second embodiment is similar except that the color code stored at the X and Y coordinates of the first date register is recalled for combining with the predetermined color code and the combined result stored at that pixel location. The predetermined color code is preferrably stored in another data register. By proper selection of the X and Y coordinate data stored in the second data register either the X or the Y coordinate may be altered alone or both may by simultaneously changed. Provision of signed X and Y coordinate values in the second register enables either the X or Y coordinate to be incremented of decremented. This instruction serves to inhance the speed at which a line or computed curve may by drawn in the bit mapped display.
摘要翻译：本发明的图形数据处理器在其指令集中作为单个指令提供绘图和提前操作。第一数据寄存器存储一组X和Y坐标。在第一实施例中，在由X和Y指示的位映射显示存储器的像素地址处存储预定色码，并且在执行绘图和提前指令时对第一数据寄存器进行坐标。然后通过加上存储在第二数据寄存器中的X和Y坐标来提前存储在第一数据寄存器中的X和Y坐标。第二实施例是类似的，除了存储在第一日期寄存器的X和Y坐标处的颜色代码被调用以与预定颜色代码组合，并且存储在该像素位置处的组合结果。预定的颜色代码优选地存储在另一个数据寄存器中。通过适当选择存储在第二数据寄存器中的X和Y坐标数据，X或Y坐标可以单独改变，或者两者可以同时改变。在第二个寄存器中提供有符号的X和Y坐标值可以使X或Y坐标递增递减。该指令用于提高在位映射显示中绘制线或计算曲线的速度。

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