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1. 发明授权

US6088280A High-speed memory arranged for operating synchronously with a microprocessor 失效
标题翻译：高速存储器布置成与微处理器同步操作
公开(公告)号：US6088280A
公开(公告)日：2000-07-11
申请号：US413928
申请日：1999-10-07
申请人： Wilbur Christian Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur Christian Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译：同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。同步随机存取存储器件可以制造为动态存储器件或静态存储器件。

2. 发明授权

US5912854A Data processing system arranged for operating synchronously with a high speed memory 失效
标题翻译：数据处理系统被布置成与高速存储器同步操作
公开(公告)号：US5912854A
公开(公告)日：1999-06-15
申请号：US905751
申请日：1997-08-04
申请人： Wilbur Christian Vogley , Anthony Michael Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur Christian Vogley , Anthony Michael Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C13/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译：同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。同步随机存取存储器件可以制造为动态存储器件或静态存储器件。

3. 发明授权

US5808958A Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock 失效
标题翻译：具有布置成与微处理器同步操作的延迟的随机存取存储器以及包括数据处理器，同步DRAM，外围设备和系统时钟的系统
公开(公告)号：US5808958A
公开(公告)日：1998-09-15
申请号：US477735
申请日：1995-06-07
申请人： Wilbur Christian Vogley , Anthony Michael Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur Christian Vogley , Anthony Michael Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译：同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。同步随机存取存储器件可以制造为动态存储器件或静态存储器件。

4. 发明授权

US5982694A High speed memory arranged for operating synchronously with a microprocessor 失效
标题翻译：高速存储器布置成与微处理器同步操作
公开(公告)号：US5982694A
公开(公告)日：1999-11-09
申请号：US747120
申请日：1996-11-08
申请人： Wilbur Christian Vogley , Anthony Michael Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur Christian Vogley , Anthony Michael Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C13/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译：同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。同步随机存取存储器件可以制造为动态存储器件或静态存储器件。

5. 发明授权

US5587954A Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock 失效
标题翻译：布置成与微处理器同步操作的随机存取存储器和包括数据处理器，同步DRAM，外围设备和系统时钟的系统
公开(公告)号：US5587954A
公开(公告)日：1996-12-24
申请号：US327540
申请日：1994-10-21
申请人： Wilbur C. Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur C. Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C13/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译：同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。同步随机存取存储器件可以制造为动态存储器件或静态存储器件。

6. 发明授权

US5390149A System including a data processor, a synchronous dram, a peripheral device, and a system clock 失效
标题翻译：系统包括数据处理器，同步电平，外围设备和系统时钟
公开(公告)号：US5390149A
公开(公告)日：1995-02-14
申请号：US184749
申请日：1994-01-21
申请人： Wilbur C. Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur C. Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C13/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译：同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。同步随机存取存储器件可以制造为动态存储器件或静态存储器件。

7. 发明授权

US5347184A Dual receiver edge-triggered digital signal level detection system 失效
标题翻译：双接收边缘触发数字信号电平检测系统
公开(公告)号：US5347184A
公开(公告)日：1994-09-13
申请号：US998166
申请日：1992-12-29
申请人： Michael C. Stephens, Jr. , Roger D. Norwood , Duy-Loan T. Le , Kenneth A. Poteet
发明人： Michael C. Stephens, Jr. , Roger D. Norwood , Duy-Loan T. Le , Kenneth A. Poteet
IPC分类号： H03K19/096 , H03K19/01
CPC分类号： H03K19/0963
摘要： Two separate receivers (120,122) receive the input signal (128) and the clock signal (126). During the inactive state of the clock signal, the first receiver produces a low state output (130) and the second receiver produces a high state output (132). Both outputs feed combinational logic (124), which produces two outputs (142,144) both normally low. Upon transition of the clock signal, the output of only one of the receivers changes state to match the logic state of the input signal. The output of the other receiver maintains its logic state. Upon the change in the clock signal, only one of the combinational logic outputs changes state to a logical high state to indicate the state of the one input signal.
摘要翻译：两个单独的接收器（120,122）接收输入信号（128）和时钟信号（126）。在时钟信号的无效状态期间，第一接收器产生低状态输出（130），第二接收器产生高状态输出（132）。两个输出都输出组合逻辑（124），其产生通常为低的两个输出（142,144）。在时钟信号转换时，只有一个接收机的输出改变状态以与输入信号的逻辑状态相匹配。另一个接收器的输出保持其逻辑状态。在时钟信号变化时，组合逻辑输出中只有一个将状态改变为逻辑高状态，以指示一个输入信号的状态。

8. 发明授权

US4876671A Semiconductor dynamic memory device with metal-level selection of page mode or nibble mode 失效
标题翻译：半导体动态存储器件，具有页面模式或半字节模式的金属级选择
公开(公告)号：US4876671A
公开(公告)日：1989-10-24
申请号：US336637
申请日：1989-04-06
申请人： Roger D. Norwood , Jino Chun , Pravin P. Patel
发明人： Roger D. Norwood , Jino Chun , Pravin P. Patel
IPC分类号： G11C11/4096
CPC分类号： G11C11/4096
摘要： A semiconductor dynamic memory device is disclosed which contains circuitry for implementing both page mode and nibble modes using a conductor level selection. A clock voltage used in column decoding and output is either coupled to or decoupled from the column strobe or CAS input by conductor, so this clock voltage is rendered either dependent on, or independent of, the cycling of the column strobe.
摘要翻译：公开了一种半导体动态存储器件，其包含使用导体电平选择来实现页模式和半字节模式的电路。在列解码和输出中使用的时钟电压或者与列选通或由输入的CAS输入耦合或分离，因此该时钟电压取决于或不依赖于列选通的循环。

9. 发明授权

US07106637B2 Asynchronous interface circuit and method for a pseudo-static memory device 有权
公开(公告)号：US07106637B2
公开(公告)日：2006-09-12
申请号：US10754658
申请日：2004-01-08
申请人： Simon J. Lovett , Cliff Zitlaw , Brian M. Shirley , Roger D. Norwood , John F. Schreck
发明人： Simon J. Lovett , Cliff Zitlaw , Brian M. Shirley , Roger D. Norwood , John F. Schreck
IPC分类号： G11C7/00
CPC分类号： G11C8/18 , G11C7/22
摘要： An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.

10. 发明授权

US5557219A Interface level programmability 失效
标题翻译：接口级可编程性
公开(公告)号：US5557219A
公开(公告)日：1996-09-17
申请号：US456436
申请日：1995-06-01
申请人： Roger D. Norwood , Brian L. Brown
发明人： Roger D. Norwood , Brian L. Brown
IPC分类号： H03K19/0185 , H03K19/173
CPC分类号： H03K19/018585
摘要： A system of interface circuits (15, 20-1 through 20-N) includes a mode sensing circuit (15) and one or more output circuits (20-1 through 20-N). The mode sensing circuit is arranged for producing control signals (on leads 22, 24) in response to an input signal (on lead 21). The output circuit (34-1) is arranged for producing an output data signal (DQ-1) dependent upon an input data signal (DATA) when the input signal (on lead 21) is in a first state and dependent upon the input data signal and the configuration of the connected output circuit (34-1) when the input signal is in a second state.
摘要翻译：接口电路（15,20-1至20-N）的系统包括模式感测电路（15）和一个或多个输出电路（20-1至20-N）。模式感测电路被布置成响应于输入信号（在引线21上）产生控制信号（在引线22,24上）。输出电路（34-1）被布置用于当输入信号（在引线21上）处于第一状态并且取决于输入数据时，根据输入数据信号（DATA）产生输出数据信号（DQ-1）信号以及当输入信号处于第二状态时连接的输出电路（34-1）的配置。

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