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1. 发明申请

US20130046934A1 SYSTEM CACHING USING HETEROGENOUS MEMORIES 审中-公开
标题翻译：使用异构记忆的系统缓存
公开(公告)号：US20130046934A1
公开(公告)日：2013-02-21
申请号：US13209439
申请日：2011-08-15
申请人： Robert Nychka , William Michael Johnson , Steven D. Krueger
发明人： Robert Nychka , William Michael Johnson , Steven D. Krueger
IPC分类号： G06F12/08
CPC分类号： G06F12/0897
摘要： A caching circuit includes tag memories for storing tagged addresses of a first cache. On-chip data memories are arranged in the same die as the tag memories, and the on-chip data memories form a first sub-hierarchy of the first cache. Off-chip data memories are arranged in a different die as the tag memories, and the off-chip data memories form a second sub-hierarchy of the first cache. Sources (such as processors) are arranged to use the tag memories to service first cache requests using the first and second sub-hierarchies of the first cache.
摘要翻译：缓存电路包括用于存储第一高速缓存的标记地址的标签存储器。片上数据存储器被布置在与标签存储器相同的芯片中，并且片上数据存储器形成第一高速缓存的第一子层。片外数据存储器被布置在不同的管芯中作为标签存储器，并且片外数据存储器形成第一高速缓存的第二子层级。源（例如处理器）被布置为使用标签存储器来使用第一高速缓存的第一和第二子层次来服务第一高速缓存请求。

2. 发明授权

US6088280A High-speed memory arranged for operating synchronously with a microprocessor 失效
标题翻译：高速存储器布置成与微处理器同步操作
公开(公告)号：US6088280A
公开(公告)日：2000-07-11
申请号：US413928
申请日：1999-10-07
申请人： Wilbur Christian Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur Christian Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译：同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。同步随机存取存储器件可以制造为动态存储器件或静态存储器件。

3. 发明授权

US5008807A Data processing apparatus with abbreviated jump field 失效
标题翻译：具有缩写跳转字段的数据处理装置
公开(公告)号：US5008807A
公开(公告)日：1991-04-16
申请号：US517979
申请日：1990-04-27
申请人： Steven D. Krueger , Michael J. Amundsen
发明人： Steven D. Krueger , Michael J. Amundsen
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32
CPC分类号： G06F9/30192 , G06F9/30069 , G06F9/30145 , G06F9/30178 , G06F9/322
摘要： The abbreviated jump field of the present invention enables each instruction word within the data processing apparatus to cause an instruction sequence branch to one of a limited number of destinations. Each instruction word of the data processing apparatus includes a limited number of bits which are decoded to specify one of a small set of instruction destinations. One of the possible destinations is the normal default destination of the next instruction word. In addition a relatively large number of branch instructions have been found to specify a rather limited number of destinations. In the preferred embodiment of the present invention the limited number of bits of the abbreviated jump field is employed to specify one of these widely used destinations. The widely used destinations may include a return instruction, a conditional skip of execution of the next instruction and various error handling and error recovery routines.
摘要翻译：本发明的缩写跳转领域使得数据处理装置内的每个指令字使得指令序列分支到有限数目的目的地之一。数据处理装置的每个指令字包括有限数量的位，其被解码以指定一小组指令目的地之一。其中一个可能的目的地是下一个指令字的正常默认目的地。此外，已经发现相对大量的分支指令指定相当有限数量的目的地。在本发明的优选实施例中，使用缩写跳转字段的有限数量的比特来指定这些广泛使用的目的地之一。广泛使用的目的地可以包括返回指令，执行下一条指令的条件跳过以及各种错误处理和错误恢复例程。

4. 发明授权

US08707013B2 On-demand predicate registers 有权
标题翻译：按需谓词寄存器
公开(公告)号：US08707013B2
公开(公告)日：2014-04-22
申请号：US12835320
申请日：2010-07-13
申请人： Jagadeesh Sankaran , Joseph R. Zbiciak , Steven D. Krueger
发明人： Jagadeesh Sankaran , Joseph R. Zbiciak , Steven D. Krueger
IPC分类号： G06F9/30
CPC分类号： G06F9/30072 , G06F9/3013 , G06F9/30138 , G06F9/30145 , G06F9/381 , G06F9/3822
摘要： In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The register set includes a plurality of legacy predicate registers. Separate from the legacy predicate registers, a plurality of on-demand predicate registers are selectively signaled without changing the opcode space for the DSP.
摘要翻译：根据至少一些实施例，数字信号处理器（DSP）包括与指令获取单元通信的指令获取单元和指令解码单元。 DSP还包括与指令解码单元通信的寄存器组和多个工作单元。寄存器集包括多个传统谓词寄存器。与传统谓词寄存器分离，选择性地发送多个按需谓词寄存器，而不改变DSP的操作码空间。

5. 发明授权

US06629187B1 Cache memory controlled by system address properties 有权
标题翻译：高速缓存由系统地址属性控制
公开(公告)号：US06629187B1
公开(公告)日：2003-09-30
申请号：US09702477
申请日：2000-10-31
申请人： Steven D. Krueger , David A. Comisky
发明人： Steven D. Krueger , David A. Comisky
IPC分类号： G06F1208
CPC分类号： G06F12/0888 , G06F9/3885 , G06F9/3891 , Y02D10/13
摘要： A digital system is provided with a microprocessor (100), a cache (120) and various memory and devices (140a-140n). Signals to control certain cache memory modes are provided by a physical address attribute memory (PAAM) (130). For devices present in the address space of the digital system that have different capabilities and characteristics, misuse is prevented by signaling an error or otherwise limiting the use of each device in response to attribute bits in the PAAM associated with the memory mapped address of the device. A memory management unit (110) with address translation capabilities and/or memory protection features may also be present, but is not required for operation of the PAAM.
摘要翻译：数字系统设置有微处理器（100），高速缓存（120）和各种存储器和设备（140a-140n）。用于控制某些高速缓冲存储器模式的信号由物理地址属性存储器（PAAM）提供（130）。对于存在于具有不同能力和特性的数字系统的地址空间中的设备，通过发送错误或以其他方式限制响应于与设备的存储器映射地址相关联的PAAM中的属性位的每个设备的使用来防止误用。具有地址转换能力和/或存储器保护特征的存储器管理单元（110）也可以存在，但是对于PAAM的操作不是必需的。

6. 发明授权

US6085269A Configurable expansion bus controller in a microprocessor-based system 失效
标题翻译：基于微处理器的系统中可配置的扩展总线控制器
公开(公告)号：US6085269A
公开(公告)日：2000-07-04
申请号：US961789
申请日：1997-10-31
申请人： Tai-Yuen Chan , Steven D. Krueger , Jonathan H. Shiell
发明人： Tai-Yuen Chan , Steven D. Krueger , Jonathan H. Shiell
IPC分类号： G06F13/36 , G06F13/38 , G06F13/40 , G06F1/00
CPC分类号： G06F13/385 , G06F13/4018
摘要： A host module (2) including a host CPU (10) and a configurable expansion bus controller (28, 28', 128) is disclosed. The expansion bus controller (28, 28', 128) is configurable by way of configuration signals (BCFG) to be operable in various bus configurations for communicating signals between a module bus (IBUS) and external buses (XPCI1, XPCI0). These modes include combining the external buses (XPCI1, XPCI0) into a single bus of the 64-bit PCI type, operating the external buses (XPCI1, XPCI0) as separate 32-bit PCI buses, as separate CardBus buses, as separate AGP buses (either at one or multiple data transfers per cycle), or as combinations thereof. Certain of the configuration signals (BCFG) are used to select the clock frequencies at which the external buses (XPCI1, XPCI0) operate, in either of the 64-bit or 32-bit PCI protocols, or in the AGP bus protocol when present. The external buses (XPCI1, XPCI0) may be operable at different speeds, and at different protocols, depending upon the state of the configuration signals (BCFG).
摘要翻译：公开了一种包括主机CPU（10）和可配置扩展总线控制器（28,28'，128）的主机模块（2）。扩展总线控制器（28,28'，128）可通过配置信号（BCFG）进行配置，以在各种总线配置中可操作，用于在模块总线（IBUS）和外部总线（XPCI1，XPCI0）之间传送信号。这些模式包括将外部总线（XPCI1，XPCI0）组合为64位PCI类型的单总线，将外部总线（XPCI1，XPCI0）作为单独的32位PCI总线作为单独的CardBus总线，作为单独的AGP总线（每个循环一次或多次数据传输），或作为其组合。某些配置信号（BCFG）用于选择外部总线（XPCI1，XPCI0）在64位或32位PCI协议中的任何时钟或AGP总线协议中存在的时钟频率。根据配置信号（BCFG）的状态，外部总线（XPCI1，XPCI0）可以以不同的速度和不同的协议操作。

7. 发明授权

US06032225A Microprocessor system with burstable, non-cacheable memory access support 失效
标题翻译：微处理器系统具有可突发，不可缓存的内存访问支持
公开(公告)号：US06032225A
公开(公告)日：2000-02-29
申请号：US769194
申请日：1996-12-18
申请人： Jonathan H. Shiell , Ashwini K. Nanda , Ian Chen , Steven D. Krueger
发明人： Jonathan H. Shiell , Ashwini K. Nanda , Ian Chen , Steven D. Krueger
IPC分类号： G06F12/08 , G06F13/28 , G06F12/00
CPC分类号： G06F13/28 , G06F12/0888
摘要： A microprocessor-based system (2) is disclosed, based on an x86-architecture microprocessor (5). The system includes a memory address space (30) and a input/output address space (40), where input/output operations are performed in an I/O mapped manner. According to a first embodiment of the invention, burstable access is performed to areas of the main memory (32) which are blocked from cache access, by the microprocessor (5) asserting the cache request signal (CACHE#) in combination with the control signal (M/IO#) indicating that an I/O operation is requested. The memory controller (10) interprets this combination as a burst request to the non-cacheable memory location (32), indicates the grant of burst access by asserting the cache acknowledge control signal (KEN#), and the burst memory access is then effected. According to a second embodiment of the invention, burst access to non-cacheable memory space (32) is acknowledged by the memory controller (60) by way of a burst acknowledge signal (BEN#) that is separate from the cache acknowledgment signal (KEN#).
摘要翻译：基于x86架构的微处理器（5）公开了一种基于微处理器的系统（2）。该系统包括存储器地址空间（30）和输入/输出地址空间（40），其中以I / O映射方式执行输入/输出操作。根据本发明的第一实施例，微处理器（5）结合控制信号来确定高速缓存请求信号（CACHE＃），对主存储器（32）的被高速缓存访问阻止的区域执行突发存取（M / IO＃），表示请求I / O操作。存储器控制器（10）将该组合解释为对非可缓存存储器位置（32）的突发请求，指示通过断言高速缓存确认控制信号（KEN＃）来准许突发存取，然后实现突发存储器访问。根据本发明的第二实施例，通过与高速缓存确认信号（KEN）分离的突发确认信号（BEN＃），由存储器控制器（60）确认对非可缓存存储器空间（32）的突发访问＃）。

8. 发明授权

US6002632A Circuits, systems, and methods with a memory interface for augmenting precharge control 有权
标题翻译：具有用于增加预充电控制的存储器接口的电路，系统和方法
公开(公告)号：US6002632A
公开(公告)日：1999-12-14
申请号：US154992
申请日：1998-09-17
申请人： Steven D. Krueger
发明人： Steven D. Krueger
IPC分类号： G11C8/00 , G11C8/12 , G11C8/18
CPC分类号： G11C8/18 , G11C8/00 , G11C8/12
摘要： A digital computing system (30). The digital computing system includes a memory (36) and a memory controller (34). The memory comprises at least one memory bank (B0), and that bank comprises a plurality of rows (R.sub.0 -R.sub.N) and a plurality of columns (C.sub.0 -C.sub.N). The memory controller circuit is coupled to control the memory, and comprises a first bus (38) for providing an address to the memory, and three additional buses (38, 40). A first of these additional buses provides a row address strobe signal (RAS*) to the memory, where assertion of the row address strobe signal represents an indication that an address on the bus is a valid row address directed to one of the plurality of rows. A second of these additional buses provides a column address strobe signal (CAS*) to the memory, where assertion of the column address strobe signal represents an indication that an address on the bus is a valid column address directed to at least one of the plurality of columns. A third of these additional buses provides a bank close signal (BC*) to the memory, where assertion of the bank close signal represents a request to the memory to immediately de-activate an active one of the plurality of rows.
摘要翻译：数字计算系统（30）。数字计算系统包括存储器（36）和存储器控制器（34）。存储器包括至少一个存储体（B0），并且该存储体包括多行（R0-RN）和多列（C0-CN）。存储器控制器电路被耦合以控制存储器，并且包括用于向存储器提供地址的第一总线（38）和三个附加总线（38,40）。这些附加总线中的第一个为存储器提供行地址选通信号（RAS *），其中行地址选通信号的断言表示总线上的地址是指向多行中的一个行的有效行地址的指示。这些附加总线中的第二个为存储器提供列地址选通信号（CAS *），其中列地址选通信号的断言表示总线上的地址是指向多个中的至少一个的有效列地址的指示的列。这些附加总线中的三分之一向存储器提供存储体闭合信号（BC *），其中存储体关闭信号的断言表示对存储器的请求，以立即取消激活多行中的活动的一行。

9. 发明授权

US5982694A High speed memory arranged for operating synchronously with a microprocessor 失效
标题翻译：高速存储器布置成与微处理器同步操作
公开(公告)号：US5982694A
公开(公告)日：1999-11-09
申请号：US747120
申请日：1996-11-08
申请人： Wilbur Christian Vogley , Anthony Michael Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur Christian Vogley , Anthony Michael Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C13/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译：同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。同步随机存取存储器件可以制造为动态存储器件或静态存储器件。

10. 发明授权

US5587954A Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock 失效
标题翻译：布置成与微处理器同步操作的随机存取存储器和包括数据处理器，同步DRAM，外围设备和系统时钟的系统
公开(公告)号：US5587954A
公开(公告)日：1996-12-24
申请号：US327540
申请日：1994-10-21
申请人： Wilbur C. Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur C. Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C13/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译：同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。同步随机存取存储器件可以制造为动态存储器件或静态存储器件。

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