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1. 发明授权

US6088280A High-speed memory arranged for operating synchronously with a microprocessor 失效
标题翻译：高速存储器布置成与微处理器同步操作
公开(公告)号：US6088280A
公开(公告)日：2000-07-11
申请号：US413928
申请日：1999-10-07
申请人： Wilbur Christian Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur Christian Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译：同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。同步随机存取存储器件可以制造为动态存储器件或静态存储器件。

2. 发明授权

US5475649A Dual-port memory has the serial register connected to the storage cells by single-sided bitlines 失效
标题翻译：双端口存储器通过单面位线将串行寄存器连接到存储单元
公开(公告)号：US5475649A
公开(公告)日：1995-12-12
申请号：US167473
申请日：1993-12-15
申请人： Anthony M. Balistreri , Andre J. Guillemaud
发明人： Anthony M. Balistreri , Andre J. Guillemaud
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C7/00 , G11C13/00
CPC分类号： G11C7/1075
摘要： A dual-port memory includes an array of dynamic storage cells and a serial register having a plurality of static stages. Each stage of the serial register is arranged for receiving a data bit from a selected storage cell of the array. A plurality of bitlines is interposed between the storage cells of the array and the stages of the serial register. At one time only a single selectable bitline is arranged for interconnecting each of the columns of storage cells with each of the stages of the serial register. Each stage of the serial register includes a latch disabling circuit for selectively enabling and disabling coupling from an output of one amplifier to an input of another amplifier. By disabling such coupling, new data easily can be written into the serial register stage. A keeper circuit in each stage of the serial register reduces power consumption.
摘要翻译：双端口存储器包括动态存储单元阵列和具有多个静态级的串行寄存器。串行寄存器的每个级被布置成从阵列的选定存储单元接收数据位。在阵列的存储单元和串行寄存器的级之间插入多个位线。一次仅设置一个可选位线，用于将每个存储单元的列与串行寄存器的每个级相互连接。串行寄存器的每个级包括一个锁存禁止电路，用于选择性地启用和禁用从一个放大器的输出到另一个放大器的输入的耦合。通过禁用这种耦合，可以将新的数据容易地写入串行寄存器阶段。串行寄存器的每个级别的保持电路可以降低功耗。

3. 发明授权

US5590083A Process of writing data from a data processor to a memory device register that is separate from the array 失效
标题翻译：将数据从数据处理器写入与阵列分离的存储器件寄存器的过程
公开(公告)号：US5590083A
公开(公告)日：1996-12-31
申请号：US4818
申请日：1993-01-15
申请人： Raymond Pinkham , Anthony M. Balistreri
发明人： Raymond Pinkham , Anthony M. Balistreri
IPC分类号： G11C7/10 , G11C8/16 , G11C7/00
CPC分类号： G11C7/109 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C8/16
摘要： A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is enabled by a special function pin in conjunction with the write enable and transfer enable function pins, each of which have their logic state latched in during the row address strobe signal. A second type of special cycle causes a multiplexer to select the contents of the color register, rather than the latched data state of the data input terminals, for the data to be written to the selected memory cells. The use of the color register may be used in conjunction with a mask register, where the writing of certain input/outputs is inhibited. In addition, a block write feature may be incorporated with the color register so that, in another type of special cycle, multiple columns per input/output can be simultaneously written with the contents of the color register. The dual port memory containing the color register thus may rapidly store a bit-mapped graphical image where areas of the image are "filled" with the same color information.
摘要翻译：公开了一种具有用于存储用于多个写周期的输入数据的片上颜色寄存器的双端口存储器。彩色寄存器在特殊周期内写入，通过特殊功能引脚与写入使能和转换使能功能引脚相结合，每个引脚在逻辑状态下都被锁存在行地址选通信号中。第二种类型的特殊周期使多路复用器选择彩色寄存器的内容，而不是数据输入端的锁存数据状态，以供将要写入所选存储单元的数据。彩色寄存器的使用可以与屏蔽寄存器一起使用，其中某些输入/输出的写入被禁止。此外，块写入特征可以与彩色寄存器结合，使得在另一种类型的特殊周期中，每个输入/输出的多个列可以与彩色寄存器的内容同时写入。因此，包含颜色寄存器的双端口存储器可以快速存储其中图像的区域以相同颜色信息“填充”的位映射图形图像。

4. 发明授权

US5390149A System including a data processor, a synchronous dram, a peripheral device, and a system clock 失效
标题翻译：系统包括数据处理器，同步电平，外围设备和系统时钟
公开(公告)号：US5390149A
公开(公告)日：1995-02-14
申请号：US184749
申请日：1994-01-21
申请人： Wilbur C. Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur C. Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C13/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译：同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。同步随机存取存储器件可以制造为动态存储器件或静态存储器件。

5. 发明申请

US20100259321A1 FIELD EFFECT TRANSISTOR HAVING A PLURALITY OF FIELD PLATES 有权
标题翻译：具有多种现场平板的场效应晶体管
公开(公告)号：US20100259321A1
公开(公告)日：2010-10-14
申请号：US12423776
申请日：2009-04-14
申请人： Hua-Quen Tserng , Deep C. Dumka , Martin E. Jones , Charles F. Campbell , Anthony M. Balistreri
发明人： Hua-Quen Tserng , Deep C. Dumka , Martin E. Jones , Charles F. Campbell , Anthony M. Balistreri
IPC分类号： H03H11/00 , H01L29/06 , H01L29/778 , H01L29/78 , H01L29/812
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/404
摘要： Embodiments include but are not limited to apparatuses and systems including a field-effect transistor switch. A field-effect transistor switch may include a first field plate coupled with a gate electrode, the first field plate disposed substantially equidistant from a source electrode and a drain electrode. The field-effect transistor switch may also include a second field plate proximately disposed to the first field plate and disposed substantially equidistant from the source electrode and the drain electrode. The first and second field plates may be configured to reduce an electric field between the source electrode and the gate electrode and between the drain electrode and the gate electrode.
摘要翻译：实施例包括但不限于包括场效应晶体管开关的装置和系统。场效应晶体管开关可以包括与栅电极耦合的第一场板，第一场板基本上与源电极和漏电极等距离设置。场效应晶体管开关还可以包括靠近第一场板并且与源电极和漏电极基本上等距离设置的第二场板。第一和第二场板可以被配置为减小源电极和栅电极之间以及漏电极和栅电极之间的电场。

6. 发明授权

US5299159A Serial register stage arranged for connection with a single bitline 失效
标题翻译：串行寄存器级，用于与单个位线连接
公开(公告)号：US5299159A
公开(公告)日：1994-03-29
申请号：US905967
申请日：1992-06-29
申请人： Anthony M. Balistreri , Andre J. Guillemaud
发明人： Anthony M. Balistreri , Andre J. Guillemaud
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C7/00
CPC分类号： G11C7/1075
摘要： A dual-port memory includes an array of dynamic storage cells and a serial register having a plurality of static stages. Each stage of the serial register is arranged for receiving a data bit from a selected storage cell of the array. A plurality of bitlines is interposed between the storage cells of the array and the stages of the serial register. At one time only a single selectable bitline is arranged for interconnecting each of the columns of storage cells with each of the stages of the serial register. Each stage of the serial register includes a latch disabling circuit for selectively enabling and disabling coupling from an output of one amplifier to an input of another amplifier. By disabling such coupling, new data easily can be written into the serial register stage. A keeper circuit in each stage of the serial register reduces power consumption.
摘要翻译：双端口存储器包括动态存储单元阵列和具有多个静态级的串行寄存器。串行寄存器的每个级被布置成从阵列的选定存储单元接收数据位。在阵列的存储单元和串行寄存器的级之间插入多个位线。一次仅设置一个可选位线，用于将每个存储单元的列与串行寄存器的每个级相互连接。串行寄存器的每个级包括一个锁存禁止电路，用于选择性地启用和禁用从一个放大器的输出到另一个放大器的输入的耦合。通过禁用这种耦合，可以将新的数据容易地写入串行寄存器阶段。串行寄存器的每个级别的保持电路可以降低功耗。

7. 发明授权

US4961171A Read/write memory having an on-chip input data register 失效
标题翻译：具有片内输入数据寄存器的读/写存储器
公开(公告)号：US4961171A
公开(公告)日：1990-10-02
申请号：US81926
申请日：1987-08-05
申请人： Raymond Pinkham , Anthony M. Balistreri
发明人： Raymond Pinkham , Anthony M. Balistreri
IPC分类号： G11C11/41 , G11C7/10 , G11C8/16 , G11C11/401
CPC分类号： G11C7/109 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C8/16
摘要： A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is enabled by a special function pin in conjunction with the write enable and transfer enable function pins, each of which have their logic state latched in during the row address strobe signal. A second type of special cycle causes a multiplexer to select the contents of the color register, rather than the latched data state of the data input terminals, for the data to be written to the selected memory cells. The use of the color register may be used in conjunction with a mask register, where the writing of certain input/outputs in inhibited. In addition, a block write feature may be incorporated with the color register so that, in another type of special cycle, multiple columns per input/output can be simulaneously written with the contents of the color register. The dual port memory containing the color register thus may rapidly store a bit-mapped graphical image where areas of the image are "filled" with the same color information.
摘要翻译：公开了一种具有用于存储用于多个写周期的输入数据的片上颜色寄存器的双端口存储器。彩色寄存器在特殊周期内写入，通过特殊功能引脚与写入使能和转换使能功能引脚相结合，每个引脚在逻辑状态下都被锁存在行地址选通信号中。第二种类型的特殊周期使多路复用器选择彩色寄存器的内容，而不是数据输入端的锁存数据状态，以供将要写入所选存储单元的数据。彩色寄存器的使用可以与屏蔽寄存器一起使用，其中某些输入/输出的写入被禁止。此外，块写特征可以与彩色寄存器结合，使得在另一类型的特殊周期中，每个输入/输出的多个列可以与彩色寄存器的内容同时写入。因此，包含颜色寄存器的双端口存储器可以快速存储其中图像的区域以相同颜色信息“填充”的位映射图形图像。

8. 发明授权

US5661692A Read/write dual port memory having an on-chip input data register 失效
标题翻译：读/写具有片上输入数据寄存器的双端口存储器
公开(公告)号：US5661692A
公开(公告)日：1997-08-26
申请号：US479321
申请日：1995-06-07
申请人： Raymond Pinkham , Anthony M. Balistreri
发明人： Raymond Pinkham , Anthony M. Balistreri
IPC分类号： G11C7/10 , G11C8/16 , G11C8/00
CPC分类号： G11C7/109 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C8/16
摘要： A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is enabled by a special function pin in conjunction with the write enable and transfer enable function pins, each of which have their logic state latched in during the row address strobe signal. A second type of special cycle causes a multiplexer to select the contents of the color register, rather than the latched data state of the data input terminals, for the data to be written to the selected memory cells. The use of the color register may be used in conjunction with a mask register, where the writing of certain input/outputs is inhibited. In addition, a block write feature may be incorporated with the color register so that, in another type of special cycle, multiple columns per input/output can be simultaneously written with the contents of the color register. The dual port memory containing the color register thus may rapidly store a bit-mapped graphical image where areas of the image are "filled" with the same color information.
摘要翻译：公开了一种具有用于存储用于多个写周期的输入数据的片上颜色寄存器的双端口存储器。彩色寄存器在特殊周期内写入，通过特殊功能引脚与写入使能和传输使能功能引脚相结合，每个引脚在逻辑状态下都被锁存在行地址选通信号中。第二种类型的特殊周期使多路复用器选择彩色寄存器的内容，而不是数据输入端的锁存数据状态，以供将要写入所选存储单元的数据。彩色寄存器的使用可以与屏蔽寄存器一起使用，其中某些输入/输出的写入被禁止。此外，块写入特征可以与彩色寄存器结合，使得在另一种类型的特殊周期中，每个输入/输出的多个列可以与彩色寄存器的内容同时写入。因此，包含颜色寄存器的双端口存储器可以快速存储其中图像的区域以相同颜色信息“填充”的位映射图形图像。

9. 发明授权

US5587954A Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock 失效
标题翻译：布置成与微处理器同步操作的随机存取存储器和包括数据处理器，同步DRAM，外围设备和系统时钟的系统
公开(公告)号：US5587954A
公开(公告)日：1996-12-24
申请号：US327540
申请日：1994-10-21
申请人： Wilbur C. Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
发明人： Wilbur C. Vogley , Anthony M. Balistreri , Karl M. Guttag , Steven D. Krueger , Duy-Loan T. Le , Joseph H. Neal , Kenneth A. Poteet , Joseph P. Hartigan , Roger D. Norwood
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C13/00
CPC分类号： G11C7/1006 , G11C7/1018 , G11C7/1072
摘要： A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.
摘要翻译：同步随机存取存储器被布置为直接响应于系统时钟信号，以与相关联的微处理器同步操作。同步随机存取存储器还被布置成除了同步随机存取操作之外，以同步脉冲串操作或同步包络操作来写入或读出数据。同步随机存取存储器件可以制造为动态存储器件或静态存储器件。

10. 发明授权

US5517609A Graphics display system using tiles of data 失效
标题翻译：图形显示系统采用瓷砖数据
公开(公告)号：US5517609A
公开(公告)日：1996-05-14
申请号：US563469
申请日：1990-08-06
申请人： Andrew J. Guillemaud , Anthony M. Balistreri , Karl M. Guttag , Richard D. Simpson
发明人： Andrew J. Guillemaud , Anthony M. Balistreri , Karl M. Guttag , Richard D. Simpson
IPC分类号： G09G5/395 , G06F15/00
CPC分类号： G09G5/395
摘要： A graphics display system includes a random access memory arranged with a split serial register and a multiplexer for coupling column of storage cells from the memory array to storage elements of the split serial register. Data stored in either a low half or a high half of the addresses of the memory array may be selectively coupled through the multiplexer to either a low half or a high half of the split serial register. For a tile oriented graphics display operation, this arrangement increases the number of choices of where within the random access memory array to store specific bits of the tile data to be displayed. Data representing a tile can be mapped into a single row of the random access memory array.
摘要翻译：图形显示系统包括布置有分离串行寄存器的随机存取存储器和用于将来自存储器阵列的存储单元列耦合到分离串行寄存器的存储元件的多路复用器。存储在存储器阵列的地址的低半或高半部的数据可以通过多路复用器选择性地耦合到分离串行寄存器的低半或高半。对于面向瓦片的图形显示操作，这种布置增加了随机存取存储器阵列内的哪里的选择的数量，以存储待显示的瓦片数据的特定位。表示瓦片的数据可以被映射到随机存取存储器阵列的单行中。

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