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1. 发明授权

US08217671B2 Parallel array architecture for constant current electro-migration stress testing 失效
标题翻译：用于恒流电迁移应力测试的并行阵列架构
公开(公告)号：US08217671B2
公开(公告)日：2012-07-10
申请号：US12492619
申请日：2009-06-26
申请人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
IPC分类号： G01R31/00
CPC分类号： G01R31/2858
摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.
摘要翻译：提供了一种用于恒流电迁移应力测试的并行阵列架构。并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分电流源逻辑。使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

2. 发明申请

US20100327892A1 Parallel Array Architecture for Constant Current Electro-Migration Stress Testing 失效
标题翻译：用于恒流电迁移应力测试的并行阵列架构
公开(公告)号：US20100327892A1
公开(公告)日：2010-12-30
申请号：US12492619
申请日：2009-06-26
申请人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
发明人： Kanak B. Agarwal , Peter A. Habitz , Jerry D. Hayes , Ying Liu , Deborah M. Massey , Alvin W. Strong
IPC分类号： G01R31/02
CPC分类号： G01R31/2858
摘要： A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic.
摘要翻译：提供了一种用于恒流电迁移应力测试的并行阵列架构。并行阵列结构包括被测器件（DUT）阵列，其具有并联耦合的多个DUT和与DUT阵列中相应的DUT相关联的多个局部加热元件。该架构还包括DUT阵列中的各个DUT隔离的DUT选择逻辑。此外，该架构包括提供参考电流并且控制通过DUT阵列中的DUT的电流的电流源逻辑，使得DUT阵列中的每个DUT具有基本上相同的电流密度，以及电流源使能逻辑，用于选择性地使能部分电流源逻辑。使用加热元件，DUT选择逻辑，电流源逻辑和电流源使能逻辑在DUT阵列的DUT上执行电迁移应力测试。

3. 发明授权

US07511378B2 Enhancement of performance of a conductive wire in a multilayered substrate 失效
标题翻译：提高多层基板中的导线的性能
公开(公告)号：US07511378B2
公开(公告)日：2009-03-31
申请号：US11442911
申请日：2006-05-30
申请人： Jason P. Gill , David L. Harmon , Deborah M. Massey , Alvin W. Strong , Timothy D. Sullivan , Junichi Furukawa
发明人： Jason P. Gill , David L. Harmon , Deborah M. Massey , Alvin W. Strong , Timothy D. Sullivan , Junichi Furukawa
IPC分类号： H01L23/48
CPC分类号： G06F17/5077 , H01L23/3677 , H01L23/522 , H01L23/5226 , H01L2924/0002 , H05K1/0201 , H05K3/0005 , H01L2924/00
摘要： An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.
摘要翻译：具有布线的电子结构以及用于限制布线中的温度梯度的结构设计的相关方法。该电子结构包括具有包括不物理接触的第一和第二线的层的衬底。由于焦耳加热相对于第一和第二导线中的电流密度，第一和第二导线适于处于升高的温度。第一导线通过存在于层之外的导电和导热结构电耦合到第二导线。第二导线的宽度被调整为将第一导线中的温度梯度限制在低于预定足够小的阈值，以便基本上减轻第一线中的电迁移的不利影响。

4. 发明申请

US20080297188A1 IC CHIP STRESS TESTING 失效
标题翻译： IC芯片应力测试
公开(公告)号：US20080297188A1
公开(公告)日：2008-12-04
申请号：US11755827
申请日：2007-05-31
申请人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
发明人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , G01R31/2875 , G01R31/2879
摘要： Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current IS to the line; and stress testing the line while applying the constant current IS such that the constant current IS is not altered by a resistance change due to an onset of electromigration.
摘要翻译：公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。该方法的一个实施例包括：对线路施加恒定电流IS; 并在施加恒定电流IS的同时对线进行应力测试，使得恒定电流IS不会由于电迁移的开始而被电阻变化所改变。

5. 发明授权

US07512506B2 IC chip stress testing 失效
标题翻译： IC芯片压力测试
公开(公告)号：US07512506B2
公开(公告)日：2009-03-31
申请号：US11755827
申请日：2007-05-31
申请人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
发明人： Oliver Aubel , Tom C. Lee , Deborah M. Massey , Travis S. Merrill , Stanley W. Polchlopek , Alvin W. Strong , Timothy D. Sullivan
IPC分类号： G06F19/00 , G01R31/26
CPC分类号： G01R31/2858 , G01R31/2875 , G01R31/2879
摘要： Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current Is to the line; and stress testing the line while applying the constant current Is such that the constant current Is is not altered by a resistance change due to an onset of electromigration.
摘要翻译：公开了用于对集成电路（IC）芯片中的线进行压力测试的方法，系统和程序产品。该方法的一个实施例包括：对线路施加恒定电流Is; 并且在施加恒定电流Is的同时对线进行应力测试，使得恒定电流Is不会由于电迁移开始时的电阻变化而改变。

6. 发明授权

US07096450B2 Enhancement of performance of a conductive wire in a multilayered substrate 失效
公开(公告)号：US07096450B2
公开(公告)日：2006-08-22
申请号：US10604165
申请日：2003-06-28
申请人： Jason P. Gill , David L. Harmon , Deborah M. Massey , Alvin W. Strong , Timothy D. Sullivan , Junichi Furukawa
发明人： Jason P. Gill , David L. Harmon , Deborah M. Massey , Alvin W. Strong , Timothy D. Sullivan , Junichi Furukawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , H01L23/3677 , H01L23/522 , H01L23/5226 , H01L2924/0002 , H05K1/0201 , H05K3/0005 , H01L2924/00
摘要： An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

7. 发明授权

US08592947B2 Thermally controlled refractory metal resistor 有权
$Thermally controlled refractory metal resistor$
标题翻译：耐热耐火金属电阻
公开(公告)号：US08592947B2
公开(公告)日：2013-11-26
申请号：US12962722
申请日：2010-12-08
申请人： Joseph M. Lukaitis , Deborah M. Massey , Timothy D. Sullivan , Ping-Chuan Wang , Kimball M. Watson
发明人： Joseph M. Lukaitis , Deborah M. Massey , Timothy D. Sullivan , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： H01L23/36
CPC分类号： H01L28/20 , H01L23/3677 , H01L23/5228 , H01L27/0211 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.
摘要翻译：制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。一个电阻器被包含在最上层的上方的层中。垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

8. 发明申请

US20120146186A1 THERMALLY CONTROLLED REFRACTORY METAL RESISTOR 有权
标题翻译：热控制的金属电阻器
公开(公告)号：US20120146186A1
公开(公告)日：2012-06-14
申请号：US12962722
申请日：2010-12-08
申请人： Joseph M. Lukaitis , Deborah M. Massey , Timothy D. Sullivan , Ping-Chuan Wang , Kimball M. Watson
发明人： Joseph M. Lukaitis , Deborah M. Massey , Timothy D. Sullivan , Ping-Chuan Wang , Kimball M. Watson
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L28/20 , H01L23/3677 , H01L23/5228 , H01L27/0211 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.
摘要翻译：制造该结构的结构和方法包括：半导体衬底，其具有限定水平方向的顶表面和从最接近半导体衬底的顶表面的最底层到距离顶表面最远的最高水平层叠的多个互连层。每个互连层包括在垂直于水平方向的垂直方向上彼此物理连接的垂直金属导体。最底层的垂直导体物理地连接到衬底的顶表面，垂直导体形成连接到半导体衬底的散热片。一个电阻器被包含在最上层的上方的层中。垂直导体在电阻器的向下垂直电阻器占位面下对准，并且每个互连级别还包括位于水平方向上并且连接到垂直导体的水平金属导体。

9. 发明申请

US20120259575A1 INTEGRATED CIRCUIT CHIP INCORPORATING A TEST CIRCUIT THAT ALLOWS FOR ON-CHIP STRESS TESTING IN ORDER TO MODEL OR MONITOR DEVICE PERFORMANCE DEGRADATION 审中-公开
标题翻译：集成电路芯片，包含允许在模型或监视器件性能下降的片上应力测试的测试电路
公开(公告)号：US20120259575A1
公开(公告)日：2012-10-11
申请号：US13082066
申请日：2011-04-07
申请人： Carole D. Graas , Deborah M. Massey , John Greg Massey , Pascal A. Nsame
发明人： Carole D. Graas , Deborah M. Massey , John Greg Massey , Pascal A. Nsame
IPC分类号： G06F19/00
CPC分类号： G01R31/30 , G01R31/3187
摘要： Disclosed is an integrated circuit chip incorporating a test circuit having multiple logic blocks. Each logic block is a matrix of individually selectable, physically different, test devices in a specific class of devices. An embedded processor ensures that specific stress conditions are selectively applied to the test devices and further controls selective testing, by a sensor system, of the test devices to determine the impact of the applied stress conditions. In a laboratory or test system environment, accelerated stress conditions are selectively applied to the test devices and the testing results are used to model device performance degradation due to class-specific failure mechanisms. In the field, stress conditions are selectively applied to test devices so as to mimic stress conditions impacting active devices in use on the same chip and the testing results are used to indirectly monitor performance degradation of the active devices due to class-specific failure mechanisms.
摘要翻译：公开了一种集成了具有多个逻辑块的测试电路的集成电路芯片。每个逻辑块是特定类别设备中可单独选择的，物理上不同的测试设备的矩阵。嵌入式处理器确保特定的应力条件被选择性地应用于测试装置，并进一步控制传感器系统对测试装置的选择性测试，以确定施加的应力条件的影响。在实验室或测试系统环境中，加速的应力条件被选择性地应用于测试设备，并且测试结果被用于由于特定于类别的故障机制而对设备性能的劣化进行建模。在现场，应力条件选择性地应用于测试装置，以便模拟影响同一芯片上使用中的有源器件的应力状况，并且测试结果用于间接地监视由于类特定故障机制而导致的有源器件的性能下降。

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