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1. 发明申请

WO2004055904A1 VERTICAL INSULATED GATE TRANSISTOR AND MANUFACTURING METHOD 审中-公开
标题翻译：垂直门式晶体管和制造方法
公开(公告)号：WO2004055904A1
公开(公告)日：2004-07-01
申请号：PCT/IB2003/006015
申请日：2003-12-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SCHMITZ, Jurriaan , HUETING, Raymond, J., E. , HIJZEN, Erwin, A. , MONTREE, Andreas, H. , IN 'T ZANDT, Michael, A., A. , KOOPS, Gerrit, E., J.
发明人： SCHMITZ, Jurriaan , HUETING, Raymond, J., E. , HIJZEN, Erwin, A. , MONTREE, Andreas, H. , IN 'T ZANDT, Michael, A., A. , KOOPS, Gerrit, E., J.
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/7827
摘要： A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.
摘要翻译：通过向漏极层（2）提供延伸穿过源极层（8）和沟道层（6）的沟槽（26）来制造垂直绝缘栅极晶体管。使用间隔物蚀刻沿着沟槽侧壁形成栅极部分（20），电介质材料（30）被填充到侧壁栅极部分（20）之间的沟槽中，并且栅极电连接层（30）形成在所述沟槽的顶部电连接所述栅极部分（20）穿过所述沟槽。

2. 发明申请

WO2004055882A1 METHOD OF MANUFACTURING A TRENCH-GATE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造TRENCH-GATE半导体器件的方法
公开(公告)号：WO2004055882A1
公开(公告)日：2004-07-01
申请号：PCT/IB2003/006014
申请日：2003-12-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HIJZEN, Erwin, A. , HUETING, Raymond, J., E. , IN 'T ZANDT, Michael, A., A.
发明人： HIJZEN, Erwin, A. , HUETING, Raymond, J., E. , IN 'T ZANDT, Michael, A., A.
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/4238 , H01L29/511 , H01L29/518
摘要： A method of making a trench MOSFET includes forming a nitride liner 50 on the sidewalls 28 of a trench and a plug of doped polysilicon 26 at the bottom of a trench. The plug of polysilicon 26 may then be oxidised to form a thick oxide plug 30 at the bottom of the trench whilst the nitride liner 50 protects the sidewalls 28 from oxidation. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.
摘要翻译：制造沟槽MOSFET的方法包括在沟槽的侧壁28上形成氮化物衬垫50，在沟槽的底部形成掺杂多晶硅26的插塞。然后可以将多晶硅26的塞子氧化以在沟槽的底部形成厚的氧化物塞30，而氮化物衬垫50保护侧壁28免受氧化。这在沟槽的底部形成厚的氧化物塞，从而减小栅极和漏极之间的电容。

3. 发明申请

WO2004095564A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR 审中-公开
标题翻译：用双极晶体管制造半导体器件的方法
公开(公告)号：WO2004095564A1
公开(公告)日：2004-11-04
申请号：PCT/IB2004/050497
申请日：2004-04-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MAGNEE, Petrus, H., C. , HUETING, Raymond, J., E. , MELAI, Joost , IN 'T ZANDT, Michael, A., A. , DONKERS, Johannes, J., T., M.
发明人： MAGNEE, Petrus, H., C. , HUETING, Raymond, J., E. , MELAI, Joost , IN 'T ZANDT, Michael, A., A. , DONKERS, Johannes, J., T., M.
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/76895 , H01L29/7378
摘要： Method of manufacturing a semiconductor device with a bipolar transistor, in which method, on a surface (3) of a silicon body comprising a surface layer (2) of a first conductivity type lying on a heavily doped contact layer (6) of the same, first conductivity type, a first layer of semiconductor material (8) is formed in which layer the base (21) is to be formed. In this method, a mask (9) is formed on the first layer of semiconductor material at the location of the base to be formed, after which non-covered parts of the first layer of semiconductor material are successively etched away and replaced by a layer of doped amorphous or polycrystalline silicon. Next, the mask is removed, whereby a window (17) is formed at the location of the base in which a second layer of semiconductor material (19) of the first conductivity type is deposited for forming the emitter (20) of the transistor. Thus a transistor is formed, the base of which is contacted by a highly conductive base contact (15) formed in the layer of doped amorphous or polycrystalline silicon.
摘要翻译：制造具有双极性晶体管的半导体器件的方法，在该方法中，在硅体的表面（3）上，该硅体包括位于其上的重掺杂接触层（6）上的第一导电类型的表面层（2），第一导电型，形成第一半导体材料层（8），其中将形成基底（21）。在该方法中，在要形成的基底的位置处，在第一半导体材料层上形成掩模（9），之后将第一半导体材料层的未覆盖部分相继蚀刻掉，并由层的掺杂非晶或多晶硅。接下来，去除掩模，由此在基底的位置处形成窗口（17），在该位置沉积第一导电类型的第二半导体材料层（19）以形成晶体管的发射极（20）。因此，形成晶体管，其基极由形成在掺杂的非晶或多晶硅层中的高导电性基极接触（15）接触。

4. 发明申请

WO2006024979A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 审中-公开
标题翻译：制造半导体器件的方法和采用这种方法获得的半导体器件
公开(公告)号：WO2006024979A1
公开(公告)日：2006-03-09
申请号：PCT/IB2005/052660
申请日：2005-08-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SURDEANU, Radu , HIJZEN, Erwin , IN 'T ZANDT, Michael, A., A. , HUETING, Raymond, J., E.
发明人： SURDEANU, Radu , HIJZEN, Erwin , IN 'T ZANDT, Michael, A., A. , HUETING, Raymond, J., E.
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/78648
摘要： The-invention relates to a method of manufacturing a semiconductor device (1.0) with a dual gate field effect transistor, in which method a semiconductor body (1) of a semiconductor material is provided at a surface thereof with a source region (2) and a drain region (3) of a first conductivity type and with a channel region (4) of a second conductivity type opposite to the first conductivity type between the source region (2) and the drain region (3) and with a first gate region (5) separated from the surface of the semiconductor body by a first gate dielectric (6) above the channel region (4) and with a second gate region (7) situated opposite to the first gate region (5) and formed within a recess (20) in an opposite surface of the semiconductor body (1) so as to be separated from the channel region (4) by a second gate dielectric (8), wherein the recess (20) is formed by means of a local change of the doping (9) of the channel region (4) and by performing an etching step starting from the opposite surface of the semiconductor body (1).
摘要翻译：本发明涉及一种制造具有双栅场效应晶体管的半导体器件（1.0）的方法，其中半导体材料的半导体本体（1）在其表面处设置有源区（2）和具有第一导电类型的漏极区域（3）和在源极区域（2）和漏极区域（3）之间具有与第一导电类型相反的第二导电类型的沟道区域（4）和第一栅极区域（5）通过沟道区域（4）上方的第一栅极电介质（6）和与第一栅极区域（5）相对的第二栅极区域（7）与半导体本体的表面分离并形成在凹槽内（20）在半导体本体（1）的相对表面上，以便通过第二栅极电介质（8）与沟道区（4）分离，其中凹部（20）通过通道区域（4）的掺杂（9），并且通过执行从f开始的蚀刻步骤离开半导体本体（1）的相对表面。

5. 发明申请

WO2004114411A1 LATERAL FIELD-EFFECT TRANSISTOR HAVING AN INSULATED TRENCH GATE ELECTRODE 审中-公开
标题翻译：具有绝缘的三通门电极的横向场效应晶体管
公开(公告)号：WO2004114411A1
公开(公告)日：2004-12-29
申请号：PCT/IB2004/001992
申请日：2004-06-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
发明人： HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/7825 , H01L29/7838
摘要： A field-effect transistor having cells (18) each having a source region (22), source body region (26), drift region (20), drain body region (28) and drain region (24) arranged longitudinally, laterally alternating with structures to achieve a reduced surface field. In embodiments, the structures can include longitudinally spaced insulated gate trenches (35) defining a gate region (31) adjacent the source or drain region (22, 24) and a longitudinally extending potential plate region (33) adjacent the drift region (20). Alternatively, a separate potential plate region (33) or a longitudinally extending semi-insulating field plate (50) may be provided adjacent the drift region (20). The transistor is suitable for bi-directional switching.
摘要翻译：一种具有单元（18）的场效应晶体管，每个单元具有源区域（22），源体区域（26），漂移区域（20），漏极体区域（28）和漏极区域（24）结构实现减少的表面场。在实施例中，结构可以包括限定邻近源极或漏极区域（22,24）的栅极区域（31）的纵向间隔开的绝缘栅极沟槽（35）和邻近漂移区域（20）的纵向延伸的电位板区域（33）。或者，可以在漂移区域（20）附近设置单独的电位板区域（33）或纵向延伸的半绝缘场板（50）。晶体管适用于双向开关。

6. 发明申请

WO2005053033A2 TRENCH MOSFET 审中-公开
公开(公告)号：WO2005053033A2
公开(公告)日：2005-06-09
申请号：PCT/IB2004/052563
申请日：2004-11-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
发明人： HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/4238
摘要： The invention relates to a trench MOSFET with drain (8), drift region (10) body (12) and source (14). In order to improve the figure of merit for use of the MOSFET as control and sync FETs, the trench (20) is partially filled with dielectric (24) adjacent to the drift region (10) and a graded doping profile is used in the drift region (10).
摘要翻译：本发明涉及一种具有漏极（8），漂移区（10）主体（12）和源极（14）的沟槽MOSFET。为了改善使用MOSFET作为控制和同步FET的品质因数，沟槽（20）部分地被与漂移区（10）相邻的电介质（24）填充，并且在漂移中使用渐变掺杂分布区域（10）。

7. 发明申请

WO2004114410A3 TRENCH MOS STRUCTURE 审中-公开
公开(公告)号：WO2004114410A3
公开(公告)日：2004-12-29
申请号：PCT/IB2004/001977
申请日：2004-06-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
发明人： HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
IPC分类号： H01L29/78
摘要： A semiconductor device has a trench (42) adjacent to a cell (18). The cell includes source and drain contact regions (26, 28), and a central body (40) of opposite conductivity type. The device is bidirectional and controls current in either direction with a relatively low on-resistance. Preferred embodiments include potential plates (60) that act together with source and drain drift regions (30, 32) to create a RESURF effect.

8. 发明申请

WO2005124872A1 NANOWIRE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：纳米半导体器件
公开(公告)号：WO2005124872A1
公开(公告)日：2005-12-29
申请号：PCT/IB2005/051843
申请日：2005-06-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HIJZEN, Erwin, A. , BAKKERS, Erik, P., A., M. , HUETING, Raymond, J., E. , BALKENENDE, Abraham, R.
发明人： HIJZEN, Erwin, A. , BAKKERS, Erik, P., A., M. , HUETING, Raymond, J., E. , BALKENENDE, Abraham, R.
IPC分类号： H01L29/775
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/0237 , H01L21/02458 , H01L21/02532 , H01L21/0254 , H01L21/02603 , H01L21/02639 , H01L21/02653 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/267 , H01L29/66666 , H01L29/78642 , H01L29/78681 , H01L29/78696 , H01L29/861 , H01L29/872 , H01L51/0048 , H01L51/0052 , H01L51/0512 , H01L2924/0002 , Y10S977/70 , Y10S977/701 , Y10S977/707 , Y10S977/72 , Y10S977/721 , Y10S977/722 , Y10S977/723 , Y10S977/742 , Y10S977/762 , Y10S977/938 , H01L2924/00
摘要： Semiconductor devices are fabricated using nanowires (16). A conductive gate (22) may be used to control conduction along the nanowires (16), in which case one of the contacts is a drain (12) and the other a source (18). The nanowires (16) may be grown in a trench or through-hole (8) in a substrate (2) or in particular in epilayer (3) on substrate (2). The gate (22) may be provided only at one end of the nanowires (16). The nanowires (16) can be of the same material along their length; alternatively different materials can be used, especially different materials adjacent to the gate (22) and between the gate (22) and the base of the trench.
摘要翻译：使用纳米线制造半导体器件（16）。可以使用导电栅极（22）来控制沿着纳米线（16）的导电，在这种情况下，一个触点是漏极（12），另一个是源极（18）。纳米线（16）可以在衬底（2）中的沟槽或通孔（8）中生长，或特别是在衬底（2）上的外延层（3）中生长。栅极（22）可以仅设置在纳米线（16）的一端。纳米线（16）沿其长度可以是相同的材料; 可以使用不同的材料，特别是与栅极（22）相邻并且在栅极（22）和沟槽的基部之间的不同材料。

9. 发明申请

WO2005006446A1 INSULATED GATE POWER SEMICONDUCTOR DEVICES 审中-公开
标题翻译：绝缘栅功率半导体器件
公开(公告)号：WO2005006446A1
公开(公告)日：2005-01-20
申请号：PCT/IB2004/002248
申请日：2004-07-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E. , HIJZEN, Erwin, A. , IN'T ZANDT, Michael, A., A.
发明人： HUETING, Raymond, J., E. , HIJZEN, Erwin, A. , IN'T ZANDT, Michael, A., A.
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/4238
摘要： A trench-gate semiconductor device (100) has a trench network (STR1, ITR1) surrounding a plurality of closed transistor cells (TCS). The trench network comprises segment trench regions (STR1) adjacent sides of the transistor cells (TCS) and intersection trench regions (ITR1) adjacent corners of the transistor cells. As shown in Figure 16 which is a section view along the line II-II of Figure 11, the intersection trench regions (ITR1) each include insulating material (21D) which extends from the bottom of the intersection trench region with a thickness which is greater than the thickness of the insulating material (21B1) at the bottom of the segment trench regions (STR1). The greater thickness of the insulating material (21D) extending from the bottom of the intersection trench regions (ITR1) is effective to increase the drain-source reverse breakdown voltage of the device (100). The insulating material (21D) which extends from the bottom of each intersection trench region (ITR1) may extend upwards to thicken the insulating material at the corners of the cells (TCS) over at least part of the vertical extent of the channel-accommodating body region (23) so as to increase the threshold voltage of the device.
摘要翻译：沟槽栅极半导体器件（100）具有围绕多个闭合晶体管单元（TCS）的沟槽网络（STR1，ITR1）。沟槽网络包括晶体管单元（TCS）的相邻侧的分段沟槽区域（STR1）和晶体管单元的相邻角的相交沟槽区域（ITR1）。如图16所示，图11是沿图11的II-II线的截面图，交叉沟槽区域（ITR1）各自包括从交叉沟槽区域的底部延伸的绝缘材料（21D），其厚度大于比在分段沟槽区域（STR1）的底部的绝缘材料（21B1）的厚度大。从交叉沟槽区域（ITR1）的底部延伸的绝缘材料（21D）的厚度越大，有助于增加器件（100）的漏 - 源反向击穿电压。从每个交叉沟槽区域（ITR1）的底部延伸的绝缘材料（21D）可以向上延伸，以在通道容纳体的垂直范围的至少一部分上的细胞（TCS）的角部处增厚绝缘材料区域（23），以便增加器件的阈值电压。

10. 发明申请

WO2005053032A2 TRENCH INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译： TRENCH绝缘栅场效应晶体管
公开(公告)号：WO2005053032A2
公开(公告)日：2005-06-09
申请号：PCT/IB2004/052562
申请日：2004-11-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
发明人： HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/4916
摘要： The invention relates to a trench MOSFET with drain (8), drain region (10) body (12) and source (14). The drain region is doped to have a high concentration gradient. A field plate electrode (34) is provided adjacent to the sub-channel region (10) and a gate electrode (32) next to the body (12).
摘要翻译：本发明涉及一种具有漏极（8），漏极区（10）主体（12）和源极（14）的沟槽MOSFET。掺杂漏极区域具有高浓度梯度。邻近子通道区域（10）设置场板电极（34）和靠近主体（12）的栅电极（32）。

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