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1. 发明申请

WO2004095564A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR 审中-公开
标题翻译：用双极晶体管制造半导体器件的方法
公开(公告)号：WO2004095564A1
公开(公告)日：2004-11-04
申请号：PCT/IB2004/050497
申请日：2004-04-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MAGNEE, Petrus, H., C. , HUETING, Raymond, J., E. , MELAI, Joost , IN 'T ZANDT, Michael, A., A. , DONKERS, Johannes, J., T., M.
发明人： MAGNEE, Petrus, H., C. , HUETING, Raymond, J., E. , MELAI, Joost , IN 'T ZANDT, Michael, A., A. , DONKERS, Johannes, J., T., M.
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/76895 , H01L29/7378
摘要： Method of manufacturing a semiconductor device with a bipolar transistor, in which method, on a surface (3) of a silicon body comprising a surface layer (2) of a first conductivity type lying on a heavily doped contact layer (6) of the same, first conductivity type, a first layer of semiconductor material (8) is formed in which layer the base (21) is to be formed. In this method, a mask (9) is formed on the first layer of semiconductor material at the location of the base to be formed, after which non-covered parts of the first layer of semiconductor material are successively etched away and replaced by a layer of doped amorphous or polycrystalline silicon. Next, the mask is removed, whereby a window (17) is formed at the location of the base in which a second layer of semiconductor material (19) of the first conductivity type is deposited for forming the emitter (20) of the transistor. Thus a transistor is formed, the base of which is contacted by a highly conductive base contact (15) formed in the layer of doped amorphous or polycrystalline silicon.
摘要翻译：制造具有双极性晶体管的半导体器件的方法，在该方法中，在硅体的表面（3）上，该硅体包括位于其上的重掺杂接触层（6）上的第一导电类型的表面层（2），第一导电型，形成第一半导体材料层（8），其中将形成基底（21）。在该方法中，在要形成的基底的位置处，在第一半导体材料层上形成掩模（9），之后将第一半导体材料层的未覆盖部分相继蚀刻掉，并由层的掺杂非晶或多晶硅。接下来，去除掩模，由此在基底的位置处形成窗口（17），在该位置沉积第一导电类型的第二半导体材料层（19）以形成晶体管的发射极（20）。因此，形成晶体管，其基极由形成在掺杂的非晶或多晶硅层中的高导电性基极接触（15）接触。

2. 发明申请

WO2004055904A1 VERTICAL INSULATED GATE TRANSISTOR AND MANUFACTURING METHOD 审中-公开
标题翻译：垂直门式晶体管和制造方法
公开(公告)号：WO2004055904A1
公开(公告)日：2004-07-01
申请号：PCT/IB2003/006015
申请日：2003-12-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SCHMITZ, Jurriaan , HUETING, Raymond, J., E. , HIJZEN, Erwin, A. , MONTREE, Andreas, H. , IN 'T ZANDT, Michael, A., A. , KOOPS, Gerrit, E., J.
发明人： SCHMITZ, Jurriaan , HUETING, Raymond, J., E. , HIJZEN, Erwin, A. , MONTREE, Andreas, H. , IN 'T ZANDT, Michael, A., A. , KOOPS, Gerrit, E., J.
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/7827
摘要： A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.
摘要翻译：通过向漏极层（2）提供延伸穿过源极层（8）和沟道层（6）的沟槽（26）来制造垂直绝缘栅极晶体管。使用间隔物蚀刻沿着沟槽侧壁形成栅极部分（20），电介质材料（30）被填充到侧壁栅极部分（20）之间的沟槽中，并且栅极电连接层（30）形成在所述沟槽的顶部电连接所述栅极部分（20）穿过所述沟槽。

3. 发明申请

WO2004055882A1 METHOD OF MANUFACTURING A TRENCH-GATE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造TRENCH-GATE半导体器件的方法
公开(公告)号：WO2004055882A1
公开(公告)日：2004-07-01
申请号：PCT/IB2003/006014
申请日：2003-12-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HIJZEN, Erwin, A. , HUETING, Raymond, J., E. , IN 'T ZANDT, Michael, A., A.
发明人： HIJZEN, Erwin, A. , HUETING, Raymond, J., E. , IN 'T ZANDT, Michael, A., A.
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/4238 , H01L29/511 , H01L29/518
摘要： A method of making a trench MOSFET includes forming a nitride liner 50 on the sidewalls 28 of a trench and a plug of doped polysilicon 26 at the bottom of a trench. The plug of polysilicon 26 may then be oxidised to form a thick oxide plug 30 at the bottom of the trench whilst the nitride liner 50 protects the sidewalls 28 from oxidation. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.
摘要翻译：制造沟槽MOSFET的方法包括在沟槽的侧壁28上形成氮化物衬垫50，在沟槽的底部形成掺杂多晶硅26的插塞。然后可以将多晶硅26的塞子氧化以在沟槽的底部形成厚的氧化物塞30，而氮化物衬垫50保护侧壁28免受氧化。这在沟槽的底部形成厚的氧化物塞，从而减小栅极和漏极之间的电容。

4. 发明申请

WO2006024979A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 审中-公开
标题翻译：制造半导体器件的方法和采用这种方法获得的半导体器件
公开(公告)号：WO2006024979A1
公开(公告)日：2006-03-09
申请号：PCT/IB2005/052660
申请日：2005-08-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SURDEANU, Radu , HIJZEN, Erwin , IN 'T ZANDT, Michael, A., A. , HUETING, Raymond, J., E.
发明人： SURDEANU, Radu , HIJZEN, Erwin , IN 'T ZANDT, Michael, A., A. , HUETING, Raymond, J., E.
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/78648
摘要： The-invention relates to a method of manufacturing a semiconductor device (1.0) with a dual gate field effect transistor, in which method a semiconductor body (1) of a semiconductor material is provided at a surface thereof with a source region (2) and a drain region (3) of a first conductivity type and with a channel region (4) of a second conductivity type opposite to the first conductivity type between the source region (2) and the drain region (3) and with a first gate region (5) separated from the surface of the semiconductor body by a first gate dielectric (6) above the channel region (4) and with a second gate region (7) situated opposite to the first gate region (5) and formed within a recess (20) in an opposite surface of the semiconductor body (1) so as to be separated from the channel region (4) by a second gate dielectric (8), wherein the recess (20) is formed by means of a local change of the doping (9) of the channel region (4) and by performing an etching step starting from the opposite surface of the semiconductor body (1).
摘要翻译：本发明涉及一种制造具有双栅场效应晶体管的半导体器件（1.0）的方法，其中半导体材料的半导体本体（1）在其表面处设置有源区（2）和具有第一导电类型的漏极区域（3）和在源极区域（2）和漏极区域（3）之间具有与第一导电类型相反的第二导电类型的沟道区域（4）和第一栅极区域（5）通过沟道区域（4）上方的第一栅极电介质（6）和与第一栅极区域（5）相对的第二栅极区域（7）与半导体本体的表面分离并形成在凹槽内（20）在半导体本体（1）的相对表面上，以便通过第二栅极电介质（8）与沟道区（4）分离，其中凹部（20）通过通道区域（4）的掺杂（9），并且通过执行从f开始的蚀刻步骤离开半导体本体（1）的相对表面。

5. 发明申请

WO2006109221A3 LATERAL BIPOLAR TRANSISTOR 审中-公开
公开(公告)号：WO2006109221A3
公开(公告)日：2006-10-19
申请号：PCT/IB2006/051045
申请日：2006-04-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MEUNIER-BEILLARD, Philippe , HUETING, Raymond, J., E. , DONKERS, Johannes, J., T., M. , HIJZEN, Erwin
发明人： MEUNIER-BEILLARD, Philippe , HUETING, Raymond, J., E. , DONKERS, Johannes, J., T., M. , HIJZEN, Erwin
IPC分类号： H01L21/331 , H01L29/735 , H01L27/06 , H01L21/8249
摘要： The invention provides a CMOS-based lateral bipolar transistor and a method of fabricating the same. A CMOS device forms the basis of the CMOS-based lateral bipolar transistor. The CMOS device is provided on a silicon, SOI or SSOI substrate and comprises a source and drain region, CMOS spacers (9, 10) and a removed gate electrode. An emitter region (41) and a collector region (45) are disposed in the source and drain regions, and a base region (43), comprising SiGe or p-type silicon, is provided adjacent to the emitter region (41) and the collector region (45). The base region (43) has a relatively large exposed area, because it is not covered by the, formerly removed, gate electrode. The base resistance may be reduced by providing a metal layer (29) and an electrical contact (33) on the exposed area of the base region (43).

6. 发明申请

WO2005053031A2 TRENCH INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：绝缘栅绝缘栅场效应晶体管
公开(公告)号：WO2005053031A2
公开(公告)日：2005-06-09
申请号：PCT/IB2004/052561
申请日：2004-11-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E.
发明人： HUETING, Raymond, J., E.
IPC分类号： H01L29/78
CPC分类号： H01L29/1095 , H01L29/0696 , H01L29/402 , H01L29/407 , H01L29/4232 , H01L29/42368 , H01L29/4238 , H01L29/7827 , H01L29/7831
摘要： The invention relates to a trench MOSFET with drain (8), sub-channel region (10) body (12) and source (14). The sub-channel region is doped to be the same conductivity type as the body (12), but of lower doping density. A field plate electrode (34) is provided adjacent to the sub-channel region (10) 10 and a gate electrode (32) next to the body (12).
摘要翻译：本发明涉及具有漏极（8），子沟道区（10）主体（12）和源极（14）的沟槽MOSFET。子沟道区被掺杂为与主体（12）相同的导电类型，但具有较低的掺杂密度。场板电极（34）与子沟道区（10）10相邻设置，并与主体（12）相邻设置栅电极（32）。

7. 发明申请

WO2004114411A1 LATERAL FIELD-EFFECT TRANSISTOR HAVING AN INSULATED TRENCH GATE ELECTRODE 审中-公开
标题翻译：具有绝缘的三通门电极的横向场效应晶体管
公开(公告)号：WO2004114411A1
公开(公告)日：2004-12-29
申请号：PCT/IB2004/001992
申请日：2004-06-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
发明人： HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/7825 , H01L29/7838
摘要： A field-effect transistor having cells (18) each having a source region (22), source body region (26), drift region (20), drain body region (28) and drain region (24) arranged longitudinally, laterally alternating with structures to achieve a reduced surface field. In embodiments, the structures can include longitudinally spaced insulated gate trenches (35) defining a gate region (31) adjacent the source or drain region (22, 24) and a longitudinally extending potential plate region (33) adjacent the drift region (20). Alternatively, a separate potential plate region (33) or a longitudinally extending semi-insulating field plate (50) may be provided adjacent the drift region (20). The transistor is suitable for bi-directional switching.
摘要翻译：一种具有单元（18）的场效应晶体管，每个单元具有源区域（22），源体区域（26），漂移区域（20），漏极体区域（28）和漏极区域（24）结构实现减少的表面场。在实施例中，结构可以包括限定邻近源极或漏极区域（22,24）的栅极区域（31）的纵向间隔开的绝缘栅极沟槽（35）和邻近漂移区域（20）的纵向延伸的电位板区域（33）。或者，可以在漂移区域（20）附近设置单独的电位板区域（33）或纵向延伸的半绝缘场板（50）。晶体管适用于双向开关。

8. 发明申请

WO2005093841A2 TRENCH INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译： TRENCH绝缘栅场效应晶体管
公开(公告)号：WO2005093841A2
公开(公告)日：2005-10-06
申请号：PCT/IB2005/051002
申请日：2005-03-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E.
发明人： HUETING, Raymond, J., E.
IPC分类号： H01L29/78
CPC分类号： H01L29/7825 , H01L29/407 , H01L29/42376 , H01L29/7831
摘要： The invention relates to a trench MOSFET with a pair of source regions (12,22) on either side of trench (10). Body regions (14, 24) and drift regions (16,26) are provided under the source regions, connected together by drain region 8 extending under the trench. Field plate (30) is provided to control the drift region. The device can operate in a bidirectional manner controlling current passing in either direction between the source regions (12, 22).
摘要翻译：本发明涉及在沟槽（10）的任一侧上具有一对源区（12,22）的沟槽MOSFET。主体区域（14,24）和漂移区域（16,26）设置在源极区域下方，通过在沟槽下方延伸的漏极区域8连接在一起。提供场板（30）以控制漂移区域。该装置可以以双向方式操作，以控制在源极区域（12,22）之间沿任一方向通过的电流。

9. 发明申请

WO2003044861A1 HETEROJUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH DEVICE 审中-公开
标题翻译：异质半导体器件及其制造方法
公开(公告)号：WO2003044861A1
公开(公告)日：2003-05-30
申请号：PCT/IB2002/004852
申请日：2002-11-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E. , SLOTBOOM, Jan, W. , VAN DEN OEVER, Leon, C., M.
发明人： HUETING, Raymond, J., E. , SLOTBOOM, Jan, W. , VAN DEN OEVER, Leon, C., M.
IPC分类号： H01L27/07
CPC分类号： H01L29/47 , H01L29/41708 , H01L29/42304 , H01L29/7378
摘要： The invention relates to a semiconductor device with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2), and a collector region (3), which are provided with respectively a first, a second, and a third connection conductor (4, 5, 6), while the bandgap of the base region (2) is lower than that of the collector region (3) or of the emitter region (1), for example owing to the use of a silicon-germanium alloy instead of pure silicon. Such a device is very fast, but its transistor shows a relatively low BVceo. In a device according to the invention, the emitter region (1) or the base region (2) comprises a sub-region (1B, 2B) with a reduced doping concentration, which sub-region (1B, 2B) is provided with a further connection conductor (4B, 5B) which forms a Schottky junction with the sub-region (1B, 2B). Such a device results in a transistor with a particularly high cut-off frequency fT but with no or hardly any reduction of the BVceo. In a preferred embodiment, the emitter region (1) and its sub-region (1B), or the base region (2) and its sub-region (2B) both border the surface of the semiconductor body (10) and the further connection conductor (4B, 5B) forms part of the first or the second connection conductor (4, 5), as applicable. The invention also comprises a method of manufacturing a device according to the invention.
摘要翻译：本发明涉及具有异质结双极的半导体器件，特别是具有发射极区域（1），基极区域（2）和集电极区域（3）的npn晶体管，它们分别设置有第一，第二和第三连接导体（4,5,6），而基极区域（2）的带隙比集电极区域（3）或发射极区域（1）的带隙低，例如由于使用的硅 - 锗合金代替纯硅。这样的器件非常快，但其晶体管显示出相对较低的BVceo。在根据本发明的装置中，发射极区域（1）或基极区域（2）包括具有降低的掺杂浓度的子区域（1B，2B），该子区域（1B，2B）设置有与所述子区域（1B，2B）形成肖特基结的另外的连接导体（4B，5B）。这种器件导致具有特别高的截止频率fT的晶体管，但是没有或几乎不减少BVceo。在优选实施例中，发射极区域（1）及其子区域（1B）或基极区域（2）及其子区域（2B）都与半导体本体（10）的表面相接触，并且另外的连接导体（4B，5B）形成第一或第二连接导体（4,5）的一部分。本发明还包括一种制造根据本发明的装置的方法。

10. 发明申请

WO2005053033A2 TRENCH MOSFET 审中-公开
公开(公告)号：WO2005053033A2
公开(公告)日：2005-06-09
申请号：PCT/IB2004/052563
申请日：2004-11-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
发明人： HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/4238
摘要： The invention relates to a trench MOSFET with drain (8), drift region (10) body (12) and source (14). In order to improve the figure of merit for use of the MOSFET as control and sync FETs, the trench (20) is partially filled with dielectric (24) adjacent to the drift region (10) and a graded doping profile is used in the drift region (10).
摘要翻译：本发明涉及一种具有漏极（8），漂移区（10）主体（12）和源极（14）的沟槽MOSFET。为了改善使用MOSFET作为控制和同步FET的品质因数，沟槽（20）部分地被与漂移区（10）相邻的电介质（24）填充，并且在漂移中使用渐变掺杂分布区域（10）。

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