专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2005096389A1 TRENCH SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING IT 审中-公开
公开(公告)号：WO2005096389A1
公开(公告)日：2005-10-13
申请号：PCT/IB2005/051056
申请日：2005-03-29
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HIJZEN, Erwin, A. , ROCHEFORT, Christelle , MEUNIER-BEILLARD, Philippe
发明人： HIJZEN, Erwin, A. , ROCHEFORT, Christelle , MEUNIER-BEILLARD, Philippe
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/66712 , H01L29/7811
摘要： A RESURF type semiconductor device is manufactured having a drift region (4) over a drain region (2). Trenches (8) are formed through openings in mask (6). A trench insulating layer (12) is deposited on the sidewalls and base of the trenches followed by an overetching step to remove the trench insulating layer (10) from the base of the trenches as well as the top of the sidewalls of the trenches adjacent to the first major surface leaving exposed silicon at the top of the sidewalls of the trench and the base of the trenches. Silicon is selectively grown plugging the trenches with silicon plug (18) leaving void (20).
摘要翻译：制造在漏区（2）上方具有漂移区（4）的RESURF型半导体器件。沟槽（8）通过掩模（6）中的开口形成。沟槽绝缘层（12）沉积在沟槽的侧壁和基底上，随后进行过蚀刻步骤以从沟槽的底部以及邻近沟槽的侧壁的顶部去除沟槽绝缘层（10）第一主表面在沟槽的侧壁的顶部和沟槽的基部处留下暴露的硅。硅被选择性地生长，用硅塞（18）将沟槽堵塞，留下空隙（20）。

2. 发明申请

WO2006025035A2 VERTICAL SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SUCH DEVICES 审中-公开
标题翻译：垂直半导体器件和制造这种器件的方法
公开(公告)号：WO2006025035A2
公开(公告)日：2006-03-09
申请号：PCT/IB2005/052873
申请日：2005-09-01
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , ROCHEFORT, Christelle , HIJZEN, Erwin, A. , MEUNIER-BEILLARD, Philippe
发明人： ROCHEFORT, Christelle , HIJZEN, Erwin, A. , MEUNIER-BEILLARD, Philippe
IPC分类号： H01L29/78 , H01L29/06 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/66712 , H01L29/7813
摘要： A vertical semiconductor device, for example a trench-gate MOSFET power transistor (1), has a drift region (12) of one conductivity type containing spaced vertical columns (30) of the opposite conductivity type for charge compensation increase of the device breakdown voltage. Insulating material (31) is provided on the sidewalls only of trenches (20) in the drift region (12) and the opposite conductivity type material is epitaxially grown from the bottom of the trenches (20). The presence of the sidewall insulating material (31) prevents any defects in the charge compensation columns crossing into the drain drift material which therefore prevents any excessive leakage currents in the device (1). The insulating material (31) also prevents epitaxial growth on the trench sidewalls and hence substantially prevents forming voids in the trenches which would lessen the accuracy of charge compensation. The epitaxial growth by this method can be well controlled and may be stopped at an upper level (21) below the top major surface (10a). Thus, for example,20 trench-gates 22, 23 may be formed in the same trenches (20) above the compensation columns (30).
摘要翻译：垂直半导体器件（例如沟槽栅极MOSFET功率晶体管（1））具有一种导电类型的漂移区（12），其包含相反导电类型的间隔开的垂直列（30），用于器件击穿电压的电荷补偿增加。仅在漂移区（12）中的沟槽（20）的侧壁上提供绝缘材料（31），并且相反导电类型的材料从沟槽（20）的底部外延生长。侧壁绝缘材料（31）的存在防止电荷补偿柱中的任何缺陷穿过漏极漂移材料，从而防止器件（1）中的任何过量泄漏电流。绝缘材料（31）还防止在沟槽侧壁上的外延生长，并因此基本上防止在沟槽中形成空隙，这会降低电荷补偿的准确性。通过该方法的外延生长可以被很好地控制，并且可以停止在顶部主表面（10a）下方的上层（21）处。因此，例如，可以在补偿柱（30）上方的相同沟槽（20）中形成20个沟槽栅极22,23。

3. 发明申请

WO2004055904A1 VERTICAL INSULATED GATE TRANSISTOR AND MANUFACTURING METHOD 审中-公开
标题翻译：垂直门式晶体管和制造方法
公开(公告)号：WO2004055904A1
公开(公告)日：2004-07-01
申请号：PCT/IB2003/006015
申请日：2003-12-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SCHMITZ, Jurriaan , HUETING, Raymond, J., E. , HIJZEN, Erwin, A. , MONTREE, Andreas, H. , IN 'T ZANDT, Michael, A., A. , KOOPS, Gerrit, E., J.
发明人： SCHMITZ, Jurriaan , HUETING, Raymond, J., E. , HIJZEN, Erwin, A. , MONTREE, Andreas, H. , IN 'T ZANDT, Michael, A., A. , KOOPS, Gerrit, E., J.
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/7827
摘要： A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.
摘要翻译：通过向漏极层（2）提供延伸穿过源极层（8）和沟道层（6）的沟槽（26）来制造垂直绝缘栅极晶体管。使用间隔物蚀刻沿着沟槽侧壁形成栅极部分（20），电介质材料（30）被填充到侧壁栅极部分（20）之间的沟槽中，并且栅极电连接层（30）形成在所述沟槽的顶部电连接所述栅极部分（20）穿过所述沟槽。

4. 发明申请

WO2005117073A2 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURE 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2005117073A2
公开(公告)日：2005-12-08
申请号：PCT/IB2005/051715
申请日：2005-05-25
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SONSKY, Jan , HIJZEN, Erwin, A. , IN 'T ZANDT, Michael, A., A.
发明人： SONSKY, Jan , HIJZEN, Erwin, A. , IN 'T ZANDT, Michael, A., A.
IPC分类号： H01L21/00
CPC分类号： H01L21/76264 , H01L21/76895 , H01L29/0653 , H01L29/404 , H01L29/407 , H01L29/42368 , H01L29/7816 , H01L29/7824 , H01L29/7835
摘要： A semiconductor device is formed with a lower field plate (32) and optional lateral field plates (34) around semiconductor (20) in which devices are formed, for example power FETs or other transistor or diode types. The semiconductor device is manufactured by forming trenches with insulated sidewalls, etching cavities (26) at the base of the trenches which join up and then filling the trenches with conductor (30).
摘要翻译：半导体器件形成有在其中形成器件的半导体（20）周围的下部场板（32）和可选的横向场板（34），例如功率FET或其它晶体管或二极管类型。通过形成具有绝缘侧壁的沟槽来制造半导体器件，在沟槽的基部处的蚀刻腔（26），其连接起来，然后用导体（30）填充沟槽。

5. 发明申请

WO2004114411A1 LATERAL FIELD-EFFECT TRANSISTOR HAVING AN INSULATED TRENCH GATE ELECTRODE 审中-公开
标题翻译：具有绝缘的三通门电极的横向场效应晶体管
公开(公告)号：WO2004114411A1
公开(公告)日：2004-12-29
申请号：PCT/IB2004/001992
申请日：2004-06-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
发明人： HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/7825 , H01L29/7838
摘要： A field-effect transistor having cells (18) each having a source region (22), source body region (26), drift region (20), drain body region (28) and drain region (24) arranged longitudinally, laterally alternating with structures to achieve a reduced surface field. In embodiments, the structures can include longitudinally spaced insulated gate trenches (35) defining a gate region (31) adjacent the source or drain region (22, 24) and a longitudinally extending potential plate region (33) adjacent the drift region (20). Alternatively, a separate potential plate region (33) or a longitudinally extending semi-insulating field plate (50) may be provided adjacent the drift region (20). The transistor is suitable for bi-directional switching.
摘要翻译：一种具有单元（18）的场效应晶体管，每个单元具有源区域（22），源体区域（26），漂移区域（20），漏极体区域（28）和漏极区域（24）结构实现减少的表面场。在实施例中，结构可以包括限定邻近源极或漏极区域（22,24）的栅极区域（31）的纵向间隔开的绝缘栅极沟槽（35）和邻近漂移区域（20）的纵向延伸的电位板区域（33）。或者，可以在漂移区域（20）附近设置单独的电位板区域（33）或纵向延伸的半绝缘场板（50）。晶体管适用于双向开关。

6. 发明申请

WO2004055883A1 METHOD OF MANUFACTURE OF A TRENCH-GATE SEMICONDUCTOR DEVICE 审中-公开
标题翻译： TRENCH-GATE半导体器件的制造方法
公开(公告)号：WO2004055883A1
公开(公告)日：2004-07-01
申请号：PCT/IB2003/006025
申请日：2003-12-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HIJZEN, Erwin, A.
发明人： HIJZEN, Erwin, A.
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/42368
摘要： A method of making a trench MOSFET includes forming a layer of porous silicon (26) at the bottom of a trench and then oxidizing the layer of porous silicon (26) to form a plug (30) at the bottom of the trench. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.
摘要翻译：制造沟槽MOSFET的方法包括在沟槽的底部形成多孔硅层（26），然后氧化多孔硅层（26），以在沟槽的底部形成插塞（30）。这在沟槽的底部形成厚的氧化物塞，从而减小栅极和漏极之间的电容。

7. 发明申请

WO2005053032A2 TRENCH INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译： TRENCH绝缘栅场效应晶体管
公开(公告)号：WO2005053032A2
公开(公告)日：2005-06-09
申请号：PCT/IB2004/052562
申请日：2004-11-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
发明人： HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/4916
摘要： The invention relates to a trench MOSFET with drain (8), drain region (10) body (12) and source (14). The drain region is doped to have a high concentration gradient. A field plate electrode (34) is provided adjacent to the sub-channel region (10) and a gate electrode (32) next to the body (12).
摘要翻译：本发明涉及一种具有漏极（8），漏极区（10）主体（12）和源极（14）的沟槽MOSFET。掺杂漏极区域具有高浓度梯度。邻近子通道区域（10）设置场板电极（34）和靠近主体（12）的栅电极（32）。

8. 发明申请

WO2004114410A2 TRENCH MOS STRUCTURE 审中-公开
标题翻译： TRENCH MOS结构
公开(公告)号：WO2004114410A2
公开(公告)日：2004-12-29
申请号：PCT/IB2004/001977
申请日：2004-06-10
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
发明人： HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
IPC分类号： H01L29/78
CPC分类号： H01L27/088 , H01L29/0692 , H01L29/1083 , H01L29/1087 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/78 , H01L29/7834 , H01L29/785
摘要： A semiconductor device has a trench (42) adjacent to a cell (18). The cell includes source and drain contact regions (26,28), and a central body (40) of opposite conductivity type. The device is bidirectional and controls current in either direction with a relatively low on-resistance. Preferred embodiments include potential plates (60) that act together with source and drain drift regions (30,32) to create a RESURF effect.
摘要翻译：半导体器件具有与电池（18）相邻的沟槽（42）。电池包括源极和漏极接触区域（26,28）以及具有相反导电类型的中心体（40）。器件是双向的，并且以相对较低的导通电阻来控制任一方向上的电流。优选实施例包括与源极和漏极漂移区（30,32）一起作用以产生RESURF效应的电位板（60）。

9. 发明申请

WO2005064687A1 SEMICONDUCTOR DEVICE COMPRISING A PN-HETEROJUNCTION 审中-公开
标题翻译：包含PN异常的半导体器件
公开(公告)号：WO2005064687A1
公开(公告)日：2005-07-14
申请号：PCT/IB2004/052864
申请日：2004-12-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HURKX, Godefridus, A., M. , AGARWAL, Prabhat , BALKENENDE, Abraham, R. , MAGNEE, Petrus, H., C. , WAGEMANS, Melanie, M., H. , BAKKERS, Erik, P., A., M. , HIJZEN, Erwin, A.
发明人： HURKX, Godefridus, A., M. , AGARWAL, Prabhat , BALKENENDE, Abraham, R. , MAGNEE, Petrus, H., C. , WAGEMANS, Melanie, M., H. , BAKKERS, Erik, P., A., M. , HIJZEN, Erwin, A.
IPC分类号： H01L29/861
CPC分类号： H01L29/8611 , B82Y10/00 , H01L29/045 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/2003 , H01L29/66136 , H01L29/66219 , H01L2924/0002 , H01L2924/00
摘要： An electric device is disclosed comprising a pn-heterojunction (4) formed by a nanowire (3) of 111-V semiconductor material and a semiconductor body (1) comprising a group IV semiconductor material. The nanowire (3) is positioned in direct contact with the surface (2) of the semiconductor body (1) and has a first conductivity type, the semiconductor body (1) has a second conductivity type opposite to the first conductivity type, the nanowire (3) forming with the semiconductor body (1) a pn-heterojunction (4). The nanowire of III-V semiconductor material can be used as a diffusion source (5) of dopant atoms into the semiconductor body. The diffused group III atoms and/or the group V atoms from the III-V material are the dopant atoms forming a region (6) in the semiconductor body in direct contact with the nanowire (3).
摘要翻译：公开了一种电子器件，其包括由111-V半导体材料的纳米线（3）形成的pn异质结（4）和包含IV族半导体材料的半导体本体（1）。纳米线（3）与半导体本体（1）的表面（2）直接接触并且具有第一导电类型，半导体本体（1）具有与第一导电类型相反的第二导电类型，纳米线（3）与半导体本体（1）形成pn异质结（4）。 III-V族半导体材料的纳米线可以用作半导体本体中掺杂剂原子的扩散源（5）。来自III-V材料的扩散的III族原子和/或V族原子是在半导体本体中与纳米线（3）直接接触形成区域（6）的掺杂剂原子。

10. 发明申请

WO2005053033A2 TRENCH MOSFET 审中-公开
公开(公告)号：WO2005053033A2
公开(公告)日：2005-06-09
申请号：PCT/IB2004/052563
申请日：2004-11-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
发明人： HUETING, Raymond, J., E. , HIJZEN, Erwin, A.
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/4238
摘要： The invention relates to a trench MOSFET with drain (8), drift region (10) body (12) and source (14). In order to improve the figure of merit for use of the MOSFET as control and sync FETs, the trench (20) is partially filled with dielectric (24) adjacent to the drift region (10) and a graded doping profile is used in the drift region (10).
摘要翻译：本发明涉及一种具有漏极（8），漂移区（10）主体（12）和源极（14）的沟槽MOSFET。为了改善使用MOSFET作为控制和同步FET的品质因数，沟槽（20）部分地被与漂移区（10）相邻的电介质（24）填充，并且在漂移中使用渐变掺杂分布区域（10）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式