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1. 发明申请

WO2009011221A1 A RESISTANCE CHANGE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF 审中-公开
标题翻译：电阻变化存储器件及其编程方法
公开(公告)号：WO2009011221A1
公开(公告)日：2009-01-22
申请号：PCT/JP2008/061935
申请日：2008-06-25
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki , NAKAI, Hiroto
发明人： TODA, Haruki , NAKAI, Hiroto
IPC分类号： G11C13/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/31 , G11C2213/32
摘要： A method of programming a resistance change memory device includes: applying program voltage pulses to a memory cell for programming a target resistance value; setting thermal relaxation times between the respective program voltage pulses; and controlling the shape of each the program voltage pulse in accordance with the present cell's resistance value determined by the preceding program voltage pulse application.
摘要翻译：一种对电阻变化存储器件进行编程的方法包括：将程序电压脉冲施加到存储器单元以编程目标电阻值; 设置各个编程电压脉冲之间的热弛豫时间; 并且根据由先前的编程电压脉冲应用确定的当前单元的电阻值来控制每个编程电压脉冲的形状。

2. 发明申请

WO2004090984A1 PHASE CHANGE MEMORY DEVICE 审中-公开
标题翻译：相变存储器件
公开(公告)号：WO2004090984A1
公开(公告)日：2004-10-21
申请号：PCT/JP2003/004275
申请日：2003-04-03
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： H01L27/10
CPC分类号： G11C13/0004 , G11C5/02 , G11C7/18 , G11C13/0007 , G11C2211/4013 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： A phase change memory device has a semiconductor substrate; a plurality of cell arrays stacked above the semiconductor substrate, each cell array having memory cells arranged in a matrix manner for storing resistance values as data that are determined by phase change of the memory cells, bit lines each commonly connecting one ends of plural memory cells arranged along a first direction of the matrix and word lines each commonly connecting the other ends of plural memory cells arranged along a second direction of the matrix; a read/write circuit formed on the semiconductor substrate as underlying the cell arrays for reading and writing data of the cell arrays; first and second vertical wirings disposed outside of first and second boundaries that define a cell layout region of the cell arrays in the first direction to connect the bit lines of the respective cell arrays to the read/write circuit; and third vertical wirings disposed outside of one of third and fourth boundaries that define the cell layout region in the second direction to connect the word lines of the respective cell arrays to the read/write circuit.
摘要翻译：相变存储器件具有半导体衬底; 多个单元阵列，堆叠在半导体衬底之上，每个单元阵列具有以矩阵方式布置的存储单元，用于存储电阻值，作为通过存储器单元的相变确定的数据，各通常连接多个存储单元的一端的位线沿着矩阵的第一方向布置，每个字线通常连接沿矩阵的第二方向布置的多个存储单元的另一端; 在半导体衬底上形成的用于读取和写入单元阵列数据的单元阵列的读/写电路; 布置在第一和第二边界之外的第一和第二垂直布线，其限定第一方向上的单元阵列的单元布局区域，以将各单元阵列的位线连接到读/写电路; 以及第三垂直布线，其布置在第三和第四边界之一之外，其限定第二方向上的单元布局区域，以将各单元阵列的字线连接到读/写电路。

3. 发明申请

WO2009050969A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：WO2009050969A1
公开(公告)日：2009-04-23
申请号：PCT/JP2008/066613
申请日：2008-09-09
申请人： KABUSHIKI KAISHA TOSHIBA , NAGASHIMA, Hiroyuki , INOUE, Hirofumi , TODA, Haruki
发明人： NAGASHIMA, Hiroyuki , INOUE, Hirofumi , TODA, Haruki
IPC分类号： G11C13/00 , H01L27/10 , H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： H01L27/101 , G11C11/5685 , G11C13/0004 , G11C13/0009 , G11C13/004 , G11C13/0064 , G11C2013/0054 , G11C2013/0073 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell.
摘要翻译：非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。脉冲发生器用于产生多种类型的写入脉冲，用于基于三进制或更高写入数据在三个或更多个阶段中改变可变电阻器的电阻。选择电路可操作以基于写地址从存储单元阵列中选择写入目标存储单元，并将从脉冲发生器产生的写入脉冲提供给所选存储单元。

4. 发明申请

WO2003085675A3 PHASE-CHANGE MEMORY DEVICE 审中-公开
公开(公告)号：WO2003085675A3
公开(公告)日：2003-10-16
申请号：PCT/JP2003/000155
申请日：2003-01-10
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： G11C11/34
摘要： A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WLand the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.

5. 发明申请

WO2008099723A1 SEMICONDUCTOR MEMORY WITH REED- SOLOMON DECODER 审中-公开
标题翻译：具有REED SOLOMON解码器的半导体存储器
公开(公告)号：WO2008099723A1
公开(公告)日：2008-08-21
申请号：PCT/JP2008/051903
申请日：2008-01-30
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/1575 , G06F11/1068 , H03M13/1515
摘要： A semiconductor memory device such as a flash memory with a memory cell array and a double-error correcting Reed-Solomon decoder, comprising: means for transforming the error location polynomial through variable transformation in order to obtain a unique coefficient depending on the syndromes; a lookup table for determining the error locations from the unique coefficient; and means for determining said unique coefficient from the syndromes through computation in a Residue Number System in order to achieve parallel processing and to reduce the quantity of computations, for example using residues through 15 and 17 when processing in GF (256)
摘要翻译：具有存储单元阵列和双误差校正里德 - 所罗门解码器的半导体存储器件，例如闪存，包括：用于通过变量变换来变换错误位置多项式以便获得独特系数取决于综合征; 一个用于从唯一系数确定错误位置的查找表; 以及用于通过残差数系统中的计算从所述综合征确定所述唯一系数以便实现并行处理并且减少计算量的装置，例如当在GF（256）中处理时使用残差15和17，

6. 发明申请

WO2012160863A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：WO2012160863A1
公开(公告)日：2012-11-29
申请号：PCT/JP2012/056788
申请日：2012-03-09
申请人： KABUSHIKI KAISHA TOSHIBA , DEGUCHI, Jun , TODA, Haruki
发明人： DEGUCHI, Jun , TODA, Haruki
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C2013/0073 , G11C2013/0085 , G11C2013/0088 , G11C2013/009 , G11C2213/71 , G11C2213/77
摘要： A semiconductor memory device comprises a memory cell array including plural memory cells provided at the intersections of plural first lines and plural second lines; and a write circuit. The write circuit, on execution of a write operation, executes a first step of applying a voltage across the first and second lines connected to a data-write-targeted, selected memory cell, and a different voltage across the first and second lines connected to a data-write-untargeted, unselected memory cell of the plural memory cells and, after execution of the first step, executes a second step of applying a voltage, required for data write, across the first and second lines connected to the selected memory cell, and bringing at least one of the first and second lines connected to the unselected memory cell into the floating state.
摘要翻译：半导体存储器件包括存储单元阵列，该存储单元阵列包括设置在多个第一线和多条第二线的交点处的多个存储单元; 和写电路。写入电路在执行写入操作时执行第一步骤，跨连接到数据写入目标的选择的存储器单元的第一和第二线路施加电压，并跨越连接到第一和第二线路的不同电压所述多个存储单元的数据写未指定的未选择的存储单元，并且在执行所述第一步骤之后，执行第二步骤，在连接到所选存储单元的第一和第二行上施加数据写入所需的电压并且将连接到未选择的存储单元的第一和第二线中的至少一个引入浮动状态。

7. 发明申请

WO2009038220A1 RESISTANCE-CHANGING MEMORY DEVICE 审中-公开
标题翻译：电阻变化存储器件
公开(公告)号：WO2009038220A1
公开(公告)日：2009-03-26
申请号：PCT/JP2008/067362
申请日：2008-09-18
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C13/0033 , G11C13/004 , G11C16/3431 , G11C2013/0047 , G11C2013/0054 , G11C2213/72
摘要： A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data.
摘要翻译：电阻变化存储器件具有存储单元的单元阵列，每个存储单元存储数据作为可逆可设置的电阻值，用于从单元阵列中的选定存储单元读取数据的读出放大器，以及电压发生器电路，在读取所选择的存储单元的数据之后，根据读取的数据，产生用于收敛该选择的存储单元的电阻状态的电压脉冲。

8. 发明申请

WO2004084228A1 PHASE CHANGE MEMORY DEVICE 审中-公开
标题翻译：相变存储器件
公开(公告)号：WO2004084228A1
公开(公告)日：2004-09-30
申请号：PCT/JP2003/003256
申请日：2003-03-18
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： G11C11/34
CPC分类号： G11C13/0004 , G11C8/08 , G11C11/36 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/009 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A phase change memory device includes a substrate, a plurality of cell arrays stacked above the substrate and each including a matrix layout of a plurality of memory cells, each the memory cell storing therein as data a resistance value determinable by a phase change, a write circuit configured to write a pair cell constituted by two neighboring memory cells within the plurality of cell arrays in such a manner as to write one of the pair cell into a high resistance value state and write the other into a low resistance value state, and a read circuit configured to read complementary resistance value states of the pair cell as a one bit of data.
摘要翻译：相变存储器件包括：衬底，堆叠在衬底上的多个单元阵列，每个单元阵列包括多个存储器单元的矩阵布局，每个存储单元存储在其中作为数据可由相变所确定的电阻值，写入电路，被配置为以多个单元阵列中的两个相邻存储单元构成的对单元，以将该单元格中的一个写入高电阻值状态，并将另一个单元写入低电阻值状态;以及读取电路被配置为将对单元的互补电阻值状态读取为一位数据。

9. 发明申请

WO2003085675A2 PHASE-CHANGE MEMORY DEVICE 审中-公开
标题翻译：相变存储器件
公开(公告)号：WO2003085675A2
公开(公告)日：2003-10-16
申请号：PCT/JP2003/000155
申请日：2003-01-10
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： G11C11/34
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C2013/0054 , G11C2013/009 , G11C2213/71 , G11C2213/72 , G11C2213/78 , G11C2213/79 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WLand the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.
摘要翻译：相变存储器件具有彼此平行延伸的多个第一布线WL，多个第二布线BL布置成与第一布线WL交叉而被分离或隔离，并且存储单元MC 设置在第一布线WL和第二布线BL的各个交叉点，并且每个布线的一端连接到第一布线WL，另一端连接到第二布线BL。存储单元MC具有可变电阻元件VR，其存储由于其结晶态和非晶态之间的相变而确定的电阻值和与可变电阻元件VR串联连接的肖特基二极管SD的信息。

10. 发明申请

WO2012128134A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：WO2012128134A1
公开(公告)日：2012-09-27
申请号：PCT/JP2012/056486
申请日：2012-03-07
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： G11C13/00 , H01L27/10 , H01L27/105 , H01L45/00
CPC分类号： G11C13/003 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C2013/0073 , G11C2213/71 , G11C2213/72 , H01L27/115
摘要： A semiconductor memory device according to the embodiment comprises a memory cell array including a memory cell layer containing plural memory cells operative to store data in accordance with different resistance states; and an access circuit operative to make access to the memory cells, the memory cell changing the resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity, the access circuit applying voltages, required for access to the memory cell, to first and second lines connected to a selected memory cell, and bringing at least one of the first and second lines connected to non-selected memory cells into the floating state to make access to the selected memory cell.
摘要翻译：根据实施例的半导体存储器件包括存储单元阵列，其包括存储单元层，该存储单元层包含多个存储单元，用于根据不同的电阻状态存储数据; 以及访问电路，其操作以访问所述存储单元，所述存储单元在施加第一极性的电压时将所述电阻状态从第一电阻状态改变为第二电阻状态，并且从所述第二电阻状态改变所述电阻状态在施加第二极性的电压的情况下，所述存取电路将访问所述存储单元所需的电压施加到连接到所选择的存储单元的第一和第二行，并且使所述第一和第连接到未选择的存储器单元的第二行进入浮置状态以访问所选存储单元。

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