专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2009011221A1 A RESISTANCE CHANGE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF 审中-公开
标题翻译：电阻变化存储器件及其编程方法
公开(公告)号：WO2009011221A1
公开(公告)日：2009-01-22
申请号：PCT/JP2008/061935
申请日：2008-06-25
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki , NAKAI, Hiroto
发明人： TODA, Haruki , NAKAI, Hiroto
IPC分类号： G11C13/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/31 , G11C2213/32
摘要： A method of programming a resistance change memory device includes: applying program voltage pulses to a memory cell for programming a target resistance value; setting thermal relaxation times between the respective program voltage pulses; and controlling the shape of each the program voltage pulse in accordance with the present cell's resistance value determined by the preceding program voltage pulse application.
摘要翻译：一种对电阻变化存储器件进行编程的方法包括：将程序电压脉冲施加到存储器单元以编程目标电阻值; 设置各个编程电压脉冲之间的热弛豫时间; 并且根据由先前的编程电压脉冲应用确定的当前单元的电阻值来控制每个编程电压脉冲的形状。

2. 发明申请

WO2009051276A1 INFORMATION PROCESSING SYSTEM 审中-公开
标题翻译：信息处理系统
公开(公告)号：WO2009051276A1
公开(公告)日：2009-04-23
申请号：PCT/JP2008/069287
申请日：2008-10-17
申请人： KABUSHIKI KAISHA TOSHIBA , NAGASHIMA, Hiroyuki , NAKAI, Hiroto
发明人： NAGASHIMA, Hiroyuki , NAKAI, Hiroto
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G06F12/0246 , G06F12/0893 , G11C11/005 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C16/3431 , G11C2213/11 , G11C2213/31 , G11C2213/34 , G11C2213/56 , G11C2213/72
摘要： An information processing system comprises a main memory operative to store data, and a control circuit operative to access the main memory for data. The main memory includes a nonvolatile semiconductor memory device containing electrically erasable programmable nonvolatile memory cells each using a variable resistor, and a DRAM arranged as a cache memory between the control circuit and the nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device has a refresh mode of rewriting stored data. The control circuit activates the nonvolatile semiconductor memory device in said refresh mode based on the number of accesses to the nonvolatile semiconductor memory device.
摘要翻译：信息处理系统包括可操作地存储数据的主存储器和可操作以访问主存储器以用于数据的控制电路。主存储器包括：非易失性半导体存储器件，其包含电可擦除的可编程非易失性存储单元，每个可擦除可编程非易失性存储单元使用可变电阻器;以及DRAM，其布置在控制电路和非易失性半导体存储器件非易失性半导体存储器件具有重写存储数据的刷新模式。控制电路基于对非易失性半导体存储器件的访问次数，在所述刷新模式下激活非易失性半导体存储器件。

3. 发明申请

WO2012049881A1 PROTECTION METHOD, DECRYPTION METHOD, PLAYER, STORAGE MEDIUM, AND ENCRYPTION APPARATUS OF DIGITAL CONTENT 审中-公开
标题翻译：保护方法，分解方法，播放器，存储介质和数字内容的加密设备
公开(公告)号：WO2012049881A1
公开(公告)日：2012-04-19
申请号：PCT/JP2011/062860
申请日：2011-05-30
申请人： KABUSHIKI KAISHA TOSHIBA , NAGAI, Yuji , SAKAMOTO, Hiroyuki , NAKAI, Hiroto , MIYATA, Seiji , MIMURA, Hideki
发明人： NAGAI, Yuji , SAKAMOTO, Hiroyuki , NAKAI, Hiroto , MIYATA, Seiji , MIMURA, Hideki
IPC分类号： G06F21/22 , G06F21/24 , H04L9/08 , H04L9/14
CPC分类号： H04L9/0833 , H04L9/0816 , H04L9/0822 , H04L9/0894 , H04L2209/60
摘要： A digital content protection method includes distributing, together with an encrypted content, an encrypted protected program key, a protected content key, and a protected code including an individual instruction code, at least some elements of which are designed according to a unique operation code specification for each content player or for each content player group.
摘要翻译：数字内容保护方法包括与加密内容一起分发加密的受保护程序密钥，受保护内容密钥和包括单独指令代码的受保护代码，其中至少一些元件根据唯一的操作代码规范设计对于每个内容播放器或每个内容播放器组。

4. 发明申请

WO2011086732A1 STORAGE DEVICE MANAGEMENT DEVICE AND METHOD FOR MANAGING STORAGE DEVICE 审中-公开
标题翻译：存储设备管理设备和用于管理存储设备的方法
公开(公告)号：WO2011086732A1
公开(公告)日：2011-07-21
申请号：PCT/JP2010/066465
申请日：2010-09-15
申请人： KABUSHIKI KAISHA TOSHIBA , NAKAI, Hiroto , KANAI, Tatsunori
发明人： NAKAI, Hiroto , KANAI, Tatsunori
IPC分类号： G06F12/16 , G06F12/00 , G06F12/02
CPC分类号： G06F12/0638
摘要： According to one embodiment, a storage device management device is connected to a random access memory, and a first storage device having a lower rewrite count upper-limit. When the random access memory includes a free region sufficient to store write data, the write data is stored onto the random access memory. Data on the random access memory selected in the descending order of elapsed time from the last access is sequentially copied onto the first storage device, and a region in the random access memory which has previously stored the copied data is released. When read data is stored on the random access memory, the read data is read from the random access memory to the processor. When the read data is stored on the first storage device, the read data is copied onto the random access memory and read from the random access memory to the processor.
摘要翻译：根据一个实施例，存储设备管理设备连接到随机存取存储器和具有较低重写计数上限的第一存储设备。当随机存取存储器包括足以存储写入数据的空闲区时，写数据被存储到随机存取存储器中。按照从上次访问经过的时间的降序选择的随机存取存储器上的数据被顺序复制到第一存储设备上，并且释放了先前存储了复制数据的随机存取存储器中的区域。当读取数据存储在随机存取存储器中时，读取的数据从随机存取存储器读取到处理器。当读取的数据存储在第一存储设备上时，将读取的数据复制到随机存取存储器中并从随机存取存储器读取到处理器。

5. 发明公开

EP2455865A1 MEMORY MANAGEMENT DEVICE 有权转让
标题翻译： SPEICHERVERWALTUNGSVORRICHTUNG
公开(公告)号：EP2455865A1
公开(公告)日：2012-05-23
申请号：EP10799661.3
申请日：2010-03-08
申请人： Kabushiki Kaisha Toshiba
发明人： KUNIMATSU, Atsushi , MIYAGAWA, Masaki , NOZUE, Hiroshi , KAWAGOME, Kazuhiro , NAKAI, Hiroto , SAKAMOTO, Hiroyuki , OWA, Tsutomu , UNESAKI, Tsutomu , NISHINO, Reina , MAEDA, Kenichi , TAKADA, Mari
IPC分类号： G06F12/16 , G06F12/00 , G06F12/02
CPC分类号： G06F3/0604 , G06F3/061 , G06F3/0631 , G06F3/0638 , G06F3/0653 , G06F3/0679 , G06F12/0223 , G06F12/0246 , G06F12/06 , G06F2212/1016 , G06F2212/1036 , G06F2212/205 , G06F2212/7201 , G06F2212/7202 , G06F2212/7208
摘要： A memory management device (1) of an example of the invention controls writing into and reading from a main memory 2 including a nonvolatile semiconductor memory (9) and a volatile semiconductor memory (8) in response to a writing request and a reading request from a processor (6a). The memory management device (1) includes a coloring information storage unit (17) that stores coloring information (14) generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory (9) and the volatile semiconductor memory (8), and a writing management unit (15) that references the coloring information (14) to determines a region into which the write target data is written from the nonvolatile semiconductor memory (9) and the volatile semiconductor memory (8).
摘要翻译：本发明实施例的存储器管理装置（1）响应写入请求和读取请求，控制从包括非易失性半导体存储器（9）和易失性半导体存储器（8）的主存储器2的写入和读出处理器（6a）。存储器管理装置（1）包括着色信息存储单元（17），该着色信息存储单元（17）存储基于要写入至少一个非易失性半导体存储器（9）和写入目标数据的写入目标数据的数据特性产生的着色信息易失性半导体存储器（8）和写入管理单元（15），其引用着色信息（14），以从非易失性半导体存储器（9）和易失性半导体存储器（8）确定写入目标数据写入的区域）。

6. 发明公开

EP2198428A1 INFORMATION PROCESSING SYSTEM 审中-公开
标题翻译：信息处理系统
公开(公告)号：EP2198428A1
公开(公告)日：2010-06-23
申请号：EP08840090.8
申请日：2008-10-17
申请人： Kabushiki Kaisha Toshiba
发明人： NAGASHIMA, Hiroyuki , NAKAI, Hiroto
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G06F12/0246 , G06F12/0893 , G11C11/005 , G11C13/0004 , G11C13/0007 , G11C13/0033 , G11C16/3431 , G11C2213/11 , G11C2213/31 , G11C2213/34 , G11C2213/56 , G11C2213/72
摘要： An information processing system comprises a main memory operative to store data, and a control circuit operative to access the main memory for data. The main memory includes a nonvolatile semiconductor memory device containing electrically erasable programmable nonvolatile memory cells each using a variable resistor, and a DRAM arranged as a cache memory between the control circuit and the nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device has a refresh mode of rewriting stored data. The control circuit activates the nonvolatile semiconductor memory device in said refresh mode based on the number of accesses to the nonvolatile semiconductor memory device.
摘要翻译：一种信息处理系统包括可操作用于存储数据的主存储器以及可操作用于访问主存储器以获得数据的控制电路。主存储器包括含有各自使用可变电阻器的电可擦除可编程非易失性存储器单元的非易失性半导体存储器件以及布置为控制电路和非易失性半导体存储器件之间的高速缓冲存储器的DRAM。非易失性半导体存储器件具有重写所存储的数据的刷新模式。控制电路基于对非易失性半导体存储器件的访问次数，以所述刷新模式启动非易失性半导体存储器件。

7. 发明授权

EP0477369B1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：EP0477369B1
公开(公告)日：1997-08-13
申请号：EP90908645.6
申请日：1990-06-08
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： IWAHASHI, Hiroshi , NAKAI, Hiroto , KANAZAWA, Kazuhisa , SATO, Isao
IPC分类号： G06F11/20 , G11C7/00 , G11C16/06
CPC分类号： G11C29/842 , G11C7/14 , G11C16/28 , G11C16/32
摘要： A semiconductor memory device comprising memory cells (M11 to Mmn) for storing binary data, and first dummy cells (DM11 to DMm1) and second dummy cells (DM12 to DMm2) corresponding to the two storage conditions of the above memory cells, wherein the storage conditions of the memory cells are compared with those of the dummy cells by first and second sense amplifiers (1, 2), and the outputs of the two sense amplifiers are compared by a third sense amplifier (3) to detect the data stored in the memory cells. This makes it possible to provide a high-speed memory device which has a reduced number of memory cells, which is highly integrated, and which develops little reading error.

8. 发明公开

EP0477369A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译： HALBLEITERSPEICHERANORDNUNG。
公开(公告)号：EP0477369A1
公开(公告)日：1992-04-01
申请号：EP90908645.6
申请日：1990-06-08
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： IWAHASHI, Hiroshi , NAKAI, Hiroto , KANAZAWA, Kazuhisa , SATO, Isao
IPC分类号： G11C16/06 , G11C17/18 , G11C11/409 , G11C11/413 , G11C29/00 , G11C7/00 , G06F11/20
CPC分类号： G11C29/842 , G11C7/14 , G11C16/28 , G11C16/32
摘要： A semiconductor memory device comprising memory cells (M11 to Mmn) for storing binary data, and first dummy cells (DM11 to DMm1) and second dummy cells (DM12 to DMm2) corresponding to the two storage conditions of the above memory cells, wherein the storage conditions of the memory cells are compared with those of the dummy cells by first and second sense amplifiers (1, 2), and the outputs of the two sense amplifiers are compared by a third sense amplifier (3) to detect the data stored in the memory cells. This makes it possible to provide a high-speed memory device which has a reduced number of memory cells, which is highly integrated, and which develops little reading error.
摘要翻译：一种半导体存储器件，包括用于存储二进制数据的存储器单元（M11至Mmn）和对应于上述存储器单元的两个存储条件的第一虚设单元（DM11至DMm1）和第二虚设单元（DM12至DMm2），其中存储器将存储单元的条件与第一和第二读出放大器（1,2）的虚拟单元的条件进行比较，并且通过第三读出放大器（3）比较两个读出放大器的输出，以检测存储在存储单元记忆细胞这使得可以提供高度集成的存储单元数量减少的高速存储器件，并且几乎没有读取错误。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式