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1. 发明申请

WO2004090984A1 PHASE CHANGE MEMORY DEVICE 审中-公开
标题翻译：相变存储器件
公开(公告)号：WO2004090984A1
公开(公告)日：2004-10-21
申请号：PCT/JP2003/004275
申请日：2003-04-03
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： H01L27/10
CPC分类号： G11C13/0004 , G11C5/02 , G11C7/18 , G11C13/0007 , G11C2211/4013 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： A phase change memory device has a semiconductor substrate; a plurality of cell arrays stacked above the semiconductor substrate, each cell array having memory cells arranged in a matrix manner for storing resistance values as data that are determined by phase change of the memory cells, bit lines each commonly connecting one ends of plural memory cells arranged along a first direction of the matrix and word lines each commonly connecting the other ends of plural memory cells arranged along a second direction of the matrix; a read/write circuit formed on the semiconductor substrate as underlying the cell arrays for reading and writing data of the cell arrays; first and second vertical wirings disposed outside of first and second boundaries that define a cell layout region of the cell arrays in the first direction to connect the bit lines of the respective cell arrays to the read/write circuit; and third vertical wirings disposed outside of one of third and fourth boundaries that define the cell layout region in the second direction to connect the word lines of the respective cell arrays to the read/write circuit.
摘要翻译：相变存储器件具有半导体衬底; 多个单元阵列，堆叠在半导体衬底之上，每个单元阵列具有以矩阵方式布置的存储单元，用于存储电阻值，作为通过存储器单元的相变确定的数据，各通常连接多个存储单元的一端的位线沿着矩阵的第一方向布置，每个字线通常连接沿矩阵的第二方向布置的多个存储单元的另一端; 在半导体衬底上形成的用于读取和写入单元阵列数据的单元阵列的读/写电路; 布置在第一和第二边界之外的第一和第二垂直布线，其限定第一方向上的单元阵列的单元布局区域，以将各单元阵列的位线连接到读/写电路; 以及第三垂直布线，其布置在第三和第四边界之一之外，其限定第二方向上的单元布局区域，以将各单元阵列的字线连接到读/写电路。

2. 发明申请

WO2009050969A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：WO2009050969A1
公开(公告)日：2009-04-23
申请号：PCT/JP2008/066613
申请日：2008-09-09
申请人： KABUSHIKI KAISHA TOSHIBA , NAGASHIMA, Hiroyuki , INOUE, Hirofumi , TODA, Haruki
发明人： NAGASHIMA, Hiroyuki , INOUE, Hirofumi , TODA, Haruki
IPC分类号： G11C13/00 , H01L27/10 , H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： H01L27/101 , G11C11/5685 , G11C13/0004 , G11C13/0009 , G11C13/004 , G11C13/0064 , G11C2013/0054 , G11C2013/0073 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell.
摘要翻译：非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。脉冲发生器用于产生多种类型的写入脉冲，用于基于三进制或更高写入数据在三个或更多个阶段中改变可变电阻器的电阻。选择电路可操作以基于写地址从存储单元阵列中选择写入目标存储单元，并将从脉冲发生器产生的写入脉冲提供给所选存储单元。

3. 发明申请

WO2008099723B1 SEMICONDUCTOR MEMORY WITH REED- SOLOMON DECODER 审中-公开
标题翻译：半导体存储器与REED- SOLOMON解码器
公开(公告)号：WO2008099723B1
公开(公告)日：2008-10-23
申请号：PCT/JP2008051903
申请日：2008-01-30
申请人： TOSHIBA KK , TODA HARUKI
发明人： TODA HARUKI
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/1575 , G06F11/1068 , H03M13/1515
摘要： A semiconductor memory device such as a flash memory with a memory cell array and a double-error correcting Reed-Solomon decoder, comprising: means for transforming the error location polynomial through variable transformation in order to obtain a unique coefficient depending on the syndromes; a lookup table for determining the error locations from the unique coefficient; and means for determining said unique coefficient from the syndromes through computation in a Residue Number System in order to achieve parallel processing and to reduce the quantity of computations, for example using residues through 15 and 17 when processing in GF (256)
摘要翻译：一种半导体存储器件，例如具有存储单元阵列的闪存和双纠错里德 - 索罗姆解码器的半导体存储器件，包括：用于通过可变变换变换误差位置多项式的装置，以便根据校正子获得独特的系数; 用于从所述唯一系数确定所述错误位置的查找表; 以及用于通过残差编号系统中的计算来确定来自综合征的所述唯一系数的装置，以便实现并行处理并减少计算量，例如当在GF（256）中处理时使用通过15和17的残差，

4. 发明申请

WO2003085675A3 PHASE-CHANGE MEMORY DEVICE 审中-公开
公开(公告)号：WO2003085675A3
公开(公告)日：2003-10-16
申请号：PCT/JP2003/000155
申请日：2003-01-10
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： G11C11/34
摘要： A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WLand the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.

5. 发明申请

WO2012160863A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：WO2012160863A1
公开(公告)日：2012-11-29
申请号：PCT/JP2012/056788
申请日：2012-03-09
申请人： KABUSHIKI KAISHA TOSHIBA , DEGUCHI, Jun , TODA, Haruki
发明人： DEGUCHI, Jun , TODA, Haruki
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C2013/0073 , G11C2013/0085 , G11C2013/0088 , G11C2013/009 , G11C2213/71 , G11C2213/77
摘要： A semiconductor memory device comprises a memory cell array including plural memory cells provided at the intersections of plural first lines and plural second lines; and a write circuit. The write circuit, on execution of a write operation, executes a first step of applying a voltage across the first and second lines connected to a data-write-targeted, selected memory cell, and a different voltage across the first and second lines connected to a data-write-untargeted, unselected memory cell of the plural memory cells and, after execution of the first step, executes a second step of applying a voltage, required for data write, across the first and second lines connected to the selected memory cell, and bringing at least one of the first and second lines connected to the unselected memory cell into the floating state.
摘要翻译：半导体存储器件包括存储单元阵列，该存储单元阵列包括设置在多个第一线和多条第二线的交点处的多个存储单元; 和写电路。写入电路在执行写入操作时执行第一步骤，跨连接到数据写入目标的选择的存储器单元的第一和第二线路施加电压，并跨越连接到第一和第二线路的不同电压所述多个存储单元的数据写未指定的未选择的存储单元，并且在执行所述第一步骤之后，执行第二步骤，在连接到所选存储单元的第一和第二行上施加数据写入所需的电压并且将连接到未选择的存储单元的第一和第二线中的至少一个引入浮动状态。

6. 发明申请

WO2012067216A1 ABSORBENT ARTICLE 审中-公开
标题翻译：吸收品
公开(公告)号：WO2012067216A1
公开(公告)日：2012-05-24
申请号：PCT/JP2011/076613
申请日：2011-11-14
申请人： UNICHARM CORPORATION , TODA, Haruki , NAKAJIMA, Kaiyou
发明人： TODA, Haruki , NAKAJIMA, Kaiyou
IPC分类号： A61F13/49 , A61F13/15 , A61F13/53
CPC分类号： A61F13/51 , A61F13/4942 , A61F13/4946 , A61F13/49473 , A61F13/495 , A61F13/532 , A61F13/5323 , A61F13/533 , A61F13/53717 , A61F13/53747 , A61F13/539 , A61F2013/530554 , A61F2013/530562 , A61F2013/530868 , A61F2013/8497
摘要： An absorbent article ensuring that even when the excreted urine diffuses by running down the wearer's skin, the skin is prevented from remaining wetted. An absorbent article 1 in which the longitudinal direction from the front side to the rear side consists of a front waist region 11, a rear waist region 12 and a crotch region 13 located between these regions and an absorbent sheet 60 between the topsheet 20 and the second sheet 50 comprising at least one liquid-pervious sheet having sandwiched thereby an absorbent polymer is present between a topsheet 20 and a second sheet 50, wherein: the second sheet 50 is higher in the liquid diffusibility than the topsheet 20; the topsheet 20, the backsheet 30, the absorption body 40 and the second sheet 50 are disposed across the front waist region 11, the crotch region 13 and the rear waist region 12; and the absorbent sheet 60 is disposed in at least a part of the rear waist region 12.
摘要翻译：一种吸收性物品，确保即使当排泄的尿液通过穿过穿着者的皮肤而扩散时，防止皮肤保持润湿。从前侧到后侧的纵向方向的吸收性物品1由位于这些区域之间的前腰围区域11，后腰围区域12和裆下区域13以及在顶片20和在顶片20和第二片50之间存在包含至少一个其中夹有吸收性聚合物的透液性片的第二片50，其中：第二片50的液体扩散性高于顶片20; 顶片20，底片30，吸收体40和第二片50跨过前腰围区域11，裆下区域13和后腰围区域12设置; 并且吸收性片材60设置在后腰围区域12的至少一部分中。

7. 发明申请

WO2009038220A1 RESISTANCE-CHANGING MEMORY DEVICE 审中-公开
标题翻译：电阻变化存储器件
公开(公告)号：WO2009038220A1
公开(公告)日：2009-03-26
申请号：PCT/JP2008/067362
申请日：2008-09-18
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C13/0033 , G11C13/004 , G11C16/3431 , G11C2013/0047 , G11C2013/0054 , G11C2213/72
摘要： A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data.
摘要翻译：电阻变化存储器件具有存储单元的单元阵列，每个存储单元存储数据作为可逆可设置的电阻值，用于从单元阵列中的选定存储单元读取数据的读出放大器，以及电压发生器电路，在读取所选择的存储单元的数据之后，根据读取的数据，产生用于收敛该选择的存储单元的电阻状态的电压脉冲。

8. 发明申请

WO2004084228A1 PHASE CHANGE MEMORY DEVICE 审中-公开
标题翻译：相变存储器件
公开(公告)号：WO2004084228A1
公开(公告)日：2004-09-30
申请号：PCT/JP2003/003256
申请日：2003-03-18
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： G11C11/34
CPC分类号： G11C13/0004 , G11C8/08 , G11C11/36 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/009 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A phase change memory device includes a substrate, a plurality of cell arrays stacked above the substrate and each including a matrix layout of a plurality of memory cells, each the memory cell storing therein as data a resistance value determinable by a phase change, a write circuit configured to write a pair cell constituted by two neighboring memory cells within the plurality of cell arrays in such a manner as to write one of the pair cell into a high resistance value state and write the other into a low resistance value state, and a read circuit configured to read complementary resistance value states of the pair cell as a one bit of data.
摘要翻译：相变存储器件包括：衬底，堆叠在衬底上的多个单元阵列，每个单元阵列包括多个存储器单元的矩阵布局，每个存储单元存储在其中作为数据可由相变所确定的电阻值，写入电路，被配置为以多个单元阵列中的两个相邻存储单元构成的对单元，以将该单元格中的一个写入高电阻值状态，并将另一个单元写入低电阻值状态;以及读取电路被配置为将对单元的互补电阻值状态读取为一位数据。

9. 发明申请

WO2003085675A2 PHASE-CHANGE MEMORY DEVICE 审中-公开
标题翻译：相变存储器件
公开(公告)号：WO2003085675A2
公开(公告)日：2003-10-16
申请号：PCT/JP2003/000155
申请日：2003-01-10
申请人： KABUSHIKI KAISHA TOSHIBA , TODA, Haruki
发明人： TODA, Haruki
IPC分类号： G11C11/34
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C2013/0054 , G11C2013/009 , G11C2213/71 , G11C2213/72 , G11C2213/78 , G11C2213/79 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WLand the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.
摘要翻译：相变存储器件具有彼此平行延伸的多个第一布线WL，多个第二布线BL布置成与第一布线WL交叉而被分离或隔离，并且存储单元MC 设置在第一布线WL和第二布线BL的各个交叉点，并且每个布线的一端连接到第一布线WL，另一端连接到第二布线BL。存储单元MC具有可变电阻元件VR，其存储由于其结晶态和非晶态之间的相变而确定的电阻值和与可变电阻元件VR串联连接的肖特基二极管SD的信息。

10. 发明申请

WO1991017544A1 SEMICONDUCTOR STORAGE DEVICE HAVING MULTIPLE PORTS 审中-公开
标题翻译：具有多个端口的半导体存储器件
公开(公告)号：WO1991017544A1
公开(公告)日：1991-11-14
申请号：PCT/JP1991000587
申请日：1991-04-30
申请人： KABUSHIKI KAISHA TOSHIBA , WATANABE, Nobuo , MAGOME, Kouichi , ABE, Katsumi , TODA, Haruki
发明人： KABUSHIKI KAISHA TOSHIBA
IPC分类号： G11C11/34
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1075 , G11C2207/107
摘要： A semiconductor storage device having multiple ports comprises a RAM having a first RAM part and a second RAM part, a SAM having a first SAM part and a second SAM part, and a transferring means capable of being changeably in a split transfer state in which the first RAM part is connected with the first SAM part and the second RAM part is connected with the second SAM part and a cross transfer state in which the first RAM part is connected with the second SAM part and the second RAM part is connected with the first SAM part.
摘要翻译：具有多个端口的半导体存储装置包括具有第一RAM部分和第二RAM部分的RAM，具有第一SAM部分和第二SAM部分的SAM，以及能够以分割传送状态改变的传送装置，其中，第一RAM部与第一SAM部连接，第二RAM部与第二SAM部连接，第二RAM部与第二SAM部连接，第二RAM部与第一SAM部连接。 SAM部分。

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