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1. 发明授权

US4451904A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4451904A
公开(公告)日：1984-05-29
申请号：US228086
申请日：1981-01-26
申请人： June Sugiura , Yasunobu Kosa , Kazuhiro Komori , Ken Uchida , Shinji Shimizu
发明人： June Sugiura , Yasunobu Kosa , Kazuhiro Komori , Ken Uchida , Shinji Shimizu
IPC分类号： H01L27/112 , G11C5/02 , G11C16/04 , G11C17/00 , H01L21/8246 , H01L21/8247 , H01L23/522 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： G11C5/02 , H01L23/522 , H01L27/115 , H01L2924/0002
摘要： A semiconductor memory device includes a number of conductive layers for bit and selection lines alternately juxtaposed on the surface of a semiconductor substrate beneath a field insulating layer, with a number of MOS type memory cells arranged between the conductive layers for the bit and selection lines.
摘要翻译：半导体存储器件包括用于位和选择线的多个导电层，其交替并置在半导体衬底的场绝缘层下的表面，多个MOS型存储单元布置在用于位和选择线的导电层之间。

2. 发明授权

US4471373A Semiconductor integrated circuit device with memory MISFETS and thin and thick gate insulator MISFETS 失效
标题翻译：具有存储器MISFETS和薄和厚栅极绝缘体MISFET的半导体集成电路器件
公开(公告)号：US4471373A
公开(公告)日：1984-09-11
申请号：US223140
申请日：1981-01-07
申请人： Shinji Shimizu , Kazuhiro Komori , Yasunobu Kosa , June Sugiura
发明人： Shinji Shimizu , Kazuhiro Komori , Yasunobu Kosa , June Sugiura
IPC分类号： H01L21/28 , H01L21/32 , H01L21/82 , H01L21/8247 , H01L27/105 , H01L29/423 , H01L29/788 , H01L29/792 , H01L27/02 , H01L29/78
CPC分类号： H01L27/11526 , H01L21/28273 , H01L21/32 , H01L21/82 , H01L27/105 , H01L27/11546 , H01L29/42364
摘要： A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.
摘要翻译：一种半导体集成电路器件及其制造方法，其中在半导体衬底的表面上形成有两层栅电极结构的MIS型存储晶体管，以及具有相对较薄的低电压的MIS型晶体管在存储晶体管的周围形成栅氧化膜和具有较厚栅极氧化膜的高压用MIS型晶体管。

3. 发明授权

US4651406A Forming memory transistors with varying gate oxide thicknesses 失效
标题翻译：形成具有不同栅极氧化物厚度的存储晶体管
公开(公告)号：US4651406A
公开(公告)日：1987-03-24
申请号：US873056
申请日：1986-06-04
申请人： Shinji Shimizu , Kazuhiro Komori , Yasunobu Kosa , June Sugiura
发明人： Shinji Shimizu , Kazuhiro Komori , Yasunobu Kosa , June Sugiura
IPC分类号： H01L21/28 , H01L21/32 , H01L21/82 , H01L21/8247 , H01L27/105 , H01L29/423 , H01L29/788 , H01L29/792 , H01L21/425
CPC分类号： H01L27/11526 , H01L21/28273 , H01L21/32 , H01L21/82 , H01L27/105 , H01L27/11546 , H01L29/42364
摘要： A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.
摘要翻译：一种半导体集成电路器件及其制造方法，其中在半导体衬底的表面上形成有两层栅电极结构的MIS型存储晶体管，以及具有相对较薄的低电压的MIS型晶体管在存储晶体管的周围形成栅氧化膜和具有较厚栅极氧化膜的高压用MIS型晶体管。

4. 发明授权

US5352620A Method of making semiconductor device with memory cells and peripheral transistors 失效
标题翻译：制造具有存储单元和外围晶体管的半导体器件的方法
公开(公告)号：US5352620A
公开(公告)日：1994-10-04
申请号：US71343
申请日：1993-06-02
申请人： Kazuhiro Komori , Kenichi Kuroda , June Sugiura
发明人： Kazuhiro Komori , Kenichi Kuroda , June Sugiura
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/105 , H01L21/70
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11546
摘要： Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.
摘要翻译：公开了一种半导体集成电路器件，其包括作为存储单元的浮动栅极的LDD结构的第一场效应晶体管和LDD结构的第二场效应晶体管作为除了存储单元之外的元件，并且被用作EPROM。作为其源极或漏极区域的一部分的第一场效应晶体管的浅的低杂质浓度区域具有比作为其源极或漏极区域的一部分的第二场效应晶体管的浅的，低杂质浓度区域的杂质浓度更高的杂质浓度。

5. 发明授权

US4663645A Semiconductor device of an LDD structure having a floating gate 失效
标题翻译：具有浮动栅极的LDD结构的半导体器件
公开(公告)号：US4663645A
公开(公告)日：1987-05-05
申请号：US736770
申请日：1985-05-22
申请人： Kazuhiro Komori , Kenichi Kuroda , June Sugiura
发明人： Kazuhiro Komori , Kenichi Kuroda , June Sugiura
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/105 , H01L29/78 , H01L29/68
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11546 , Y10S257/90
摘要： A semiconductor integrated circuit device is provided which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells. A shallow, low impurity concentration region of the first field effect transistor which is a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor which is a part of its source or drain region. The device is particularly useful in an EPROM arrangement.
摘要翻译：提供一种半导体集成电路器件，其包括作为存储单元的浮动栅极的LDD结构的第一场效应晶体管和作为存储单元之外的元件的LDD结构的第二场效应晶体管。作为其源极或漏极区域的一部分的第一场效应晶体管的浅的低杂质浓度区域具有比作为其源极的一部分的第二场效应晶体管的浅的低杂质浓度区域更高的杂质浓度，或漏区。该装置在EPROM装置中特别有用。

6. 发明授权

US5194924A Semiconductor device of an LDD structure having a floating gate 失效
标题翻译：具有浮动栅极的LDD结构的半导体器件
公开(公告)号：US5194924A
公开(公告)日：1993-03-16
申请号：US781592
申请日：1991-10-23
申请人： Kazuhiro Komori , Kenichi Kuroda , June Sugiura
发明人： Kazuhiro Komori , Kenichi Kuroda , June Sugiura
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11546
摘要： Disclosed is a semiconductor integrated circuit device which includes first field effect transistors with an LDD structure having a floating gate in memory cells and second field effect transistors with an LDD structure as elements other than memory cells, and which is used as an EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.
摘要翻译：公开了一种半导体集成电路器件，其包括具有在存储器单元中具有浮动栅极的LDD结构的第一场效应晶体管和具有作为除了存储器单元之外的元素的LDD结构的第二场效应晶体管，并且被用作EPROM。作为其源极或漏极区域的一部分的第一场效应晶体管的浅的低杂质浓度区域具有比作为其源极或漏极区域的一部分的第二场效应晶体管的浅的，低杂质浓度区域的杂质浓度更高的杂质浓度。

7. 发明授权

US5098855A Semiconductor device and method of producing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5098855A
公开(公告)日：1992-03-24
申请号：US479151
申请日：1990-03-28
申请人： Kazuhiro Komori , Kenichi Kuroda , June Sugiura
发明人： Kazuhiro Komori , Kenichi Kuroda , June Sugiura
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11546 , Y10S257/90
摘要： Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of a LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.

8. 发明授权

US4918501A Semiconductor device and method of producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4918501A
公开(公告)日：1990-04-17
申请号：US291647
申请日：1988-12-29
申请人： Kazuhiro Komori , Kenichi Kuroda , June Sugiura
发明人： Kazuhiro Komori , Kenichi Kuroda , June Sugiura
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11546 , Y10S257/90
摘要： Disclosed is a semiconductor integrated circuit device which includes first field effect transistors of an LDD structure having a floating gate as memory cells and second field effect transistors of the LDD structure as elements other than the memory cells, and which is used as EPROM. A shallow, low impurity concentration region of the first field effect transistor as a part of its source or drain region has a higher impurity concentration than a shallow, low impurity concentration region of the second field effect transistor as a part of its source or drain region.
摘要翻译：公开了一种半导体集成电路器件，其包括作为存储单元的浮动栅极的LDD结构的第一场效应晶体管和LDD结构的第二场效应晶体管作为除了存储单元之外的元件，并且被用作EPROM。作为其源极或漏极区域的一部分的第一场效应晶体管的浅的低杂质浓度区域具有比作为其源极或漏极区域的一部分的第二场效应晶体管的浅的，低杂质浓度区域的杂质浓度更高的杂质浓度。

9. 发明授权

US4872041A Semiconductor device equipped with a field effect transistor having a floating gate 失效
标题翻译：配备有具有浮动栅极的场效应晶体管的半导体器件
公开(公告)号：US4872041A
公开(公告)日：1989-10-03
申请号：US161433
申请日：1988-02-24
申请人： June Sugiura , Kazuhiro Komori
发明人： June Sugiura , Kazuhiro Komori
IPC分类号： H01L27/112 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/7881 , Y10S257/90
摘要： Disclosed is a semiconductor device, and method of manufacture thereof, the device having a conductive layer formed on a semiconductor substrate, with an insulating layer interposed between the substrate and conductive layer, and wherein a dense insulating layer is disposed at the sides of the conductive layer so as to cover the sides of the insulating layer on the substrate, the dense insulating layer acting to increase retention of charge in the conductive layer. The conductive layer can be the floating gate of a field effect transistor, with a control gate formed on the floating gate via another insulating layer whose sides can also be covered by the dense insulating layer. Such field effect transistor, having the floating gate, can be used as the memory cell of an EPROM, with the charge being the data stored in the cell. A field effect transistor of a peripheral circuit of the EPROM can also have the dense insulating layer applied so as to cover the sides of the gate oxide layer thereof.
摘要翻译：公开了一种半导体器件及其制造方法，该器件具有形成在半导体衬底上的导电层，绝缘层介于衬底和导电层之间，并且其中致密绝缘层设置在导电层的侧面层，以覆盖基板上的绝缘层的侧面，致密绝缘层用于增加导电层中电荷的保留。导电层可以是场效应晶体管的浮动栅极，其中控制栅极通过另一绝缘层形成在浮置栅极上，其另一绝缘层也可以由致密绝缘层覆盖。具有浮置栅极的这种场效应晶体管可以用作EPROM的存储单元，其中电荷是存储在单元中的数据。 EPROM的外围电路的场效应晶体管也可以具有施加的致密绝缘层，以覆盖其栅极氧化物层的侧面。

10. 发明授权

US4731642A Semiconductor memory device with means to prevent word line breakage 失效
标题翻译：半导体存储器件具有防止字线破损的手段
公开(公告)号：US4731642A
公开(公告)日：1988-03-15
申请号：US704572
申请日：1985-02-22
申请人： Hisao Katto , June Sugiura , Nozomi Horino , Akira Endo , Yoshiharu Takeuchi , Yuji Arakawa
发明人： Hisao Katto , June Sugiura , Nozomi Horino , Akira Endo , Yoshiharu Takeuchi , Yuji Arakawa
IPC分类号： G11C11/401 , G11C5/02 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/10 , H01L27/108 , H01L29/78 , H01L23/50 , H01L23/54 , H01L29/44
CPC分类号： H01L23/522 , G11C5/025 , H01L27/10805 , H01L2924/0002 , Y10S257/922 , Y10S257/925 , Y10S438/926
摘要： A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.
摘要翻译：一种半导体存储器件，其具有在存储单元阵列的末端或与虚设单元阵列的字线相邻的字线旁边的布线，以防止这种字线断裂或变形。布线与电路操作无关，但是具有固定电位，并且通过形成字线的步骤形成。布线使得对相邻字线施加的处理条件与应用于其它字线的处理条件相同。

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