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1. 发明公开

CN1036297A 两极管钼-铜引线的制作方法无效
公开(公告)号：CN1036297A
公开(公告)日：1989-10-11
申请号：CN88101830
申请日：1988-03-30
申请人：上海航空公司
发明人：彭家骥
IPC分类号： H01L21/48 , H01L21/60 , H01L23/54
CPC分类号： H01L2224/43 , H01L2224/43848 , H01L2224/45 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01011 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01082 , H01L2224/48 , H01L2924/20109 , H01L2924/2011 , H01L2924/00012
摘要：本发明涉及晶体管，更具体地说涉及两极管钼-铜引线的制作方法。本发明包括由钼杆盘料采用无余量切割落料，化学处理，振动微切削。端面研磨以及钼柱与锆-铜丝焊接。由于本发明采用化学处理与机械加工相结合的处理方式，使产品的尺寸精度、光洁度、光亮度等方面的要求得到了满足。并且可以制作出价格低廉、质量符合要求的两极管钼-铜引线。

2. 发明公开

CN87107402A 半导体器件失效
公开(公告)号：CN87107402A
公开(公告)日：1988-06-22
申请号：CN87107402
申请日：1987-12-12
申请人：株式会社东芝
发明人：薄田修
IPC分类号： H01L29/40 , H01L23/54 , H01L21/28
CPC分类号： H01L24/05 , H01L23/53223 , H01L23/53242 , H01L23/53247 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05082 , H01L2224/05124 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/05172 , H01L2224/05181 , H01L2224/05556 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4807 , H01L2224/48091 , H01L2224/48453 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48724 , H01L2224/48744 , H01L2224/48747 , H01L2224/48844 , H01L2224/48847 , H01L2224/85201 , H01L2224/85205 , H01L2924/00011 , H01L2924/01005 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01073 , H01L2924/01079 , H01L2924/20106 , H01L2924/20107 , H01L2924/20108 , H01L2924/20109 , H01L2924/00014 , H01L2924/00 , H01L2224/48824 , H01L2924/00015 , H01L2924/01006
摘要：在把铜或铜合金焊接引线(16)压焊到半导体元件(13)的电极压焊区(21)上的半导体器件中，电极压焊区(21)由与半导体元件形成欧姆接触的第一金属层(18)，其硬度足以在引线焊接时不产生变形的第二金属层(19)以及用于焊接铜引线的第三金属层(20)构成，结果抑制了焊接部位电学性能的变化，并在引线焊接时抑制在半导体元件中产生应力。

3. 发明公开

CN85103501A 半导体装置的导线材料失效
公开(公告)号：CN85103501A
公开(公告)日：1986-11-12
申请号：CN85103501
申请日：1985-05-03
申请人：株式会社神户制钢所
发明人：官藤元久 , 松井隆 , 原田英和
IPC分类号： H01L23/54 , H01L23/48 , H01B1/02
CPC分类号： H01L2924/0002 , H01L2924/00
摘要：一种用于半导体装置的导线材料，组成的物质按重量计包括：Ni0.4至4.0％、Si0.1至1.0％、Zn0.05％至1.0％、Mn0.01至1.0％、Mg0.001至0.01％以下、Cr0.001至0.01％以下、S最多高达0.003％、余下的是Cu和不可避免的杂质。此外，这导线材料还可含有高达5ppm的氧及高达5ppm的氢。

4. 发明公开

CN85103269A 抗辐射半导体器件失效
公开(公告)号：CN85103269A
公开(公告)日：1986-10-29
申请号：CN85103269
申请日：1985-04-29
申请人：株式会社日立制作所
发明人：樱井博司
IPC分类号： H01L29/02 , H01L23/54
摘要：本发明涉及抗辐射半导体器件，该器件的电特性不会由于辐射而衰变。本发明提出用以构成某种电导类型而掺入半导体内的杂质应选用相应元素的一种同位素，其热中子吸收截面较小的一种，例如，用原子质量数为11的硼原子作为受主杂质，用原子质量数为123的锑Sb作为施主杂质。当用射线辐照时，该杂质所经受的原子核反应大大小于其它同位素，因而，其杂质浓度变化甚小，所以电特性不会发生变化。

5. 发明申请

WO1987000689A1 DEVICE FOR HARDENING, BY MEANS OF INSERTS, AN ELECTRICAL COMPONENT TO PROTECT IT AGAINST RADIATIONS 审中-公开
标题翻译：通过插件方式进行硬化的设备，防止辐射的电气部件
公开(公告)号：WO1987000689A1
公开(公告)日：1987-01-29
申请号：PCT/FR1986000232
申请日：1986-07-01
申请人： COMPAGNIE D'INFORMATIQUE MILITAIRE SPATIALE ET ... , VAL, Christian
发明人： COMPAGNIE D'INFORMATIQUE MILITAIRE SPATIALE ET ...
IPC分类号： H01L23/54
CPC分类号： H01L23/552 , H01L2924/16152
摘要： Hardening device comprising at least two materials, one of them having a number of atomic charges (Z) with respect to the other material. One of said materials is provided in the form of inserts placed into a layer formed by the other material. The hardening device is then obtained by piling such layers, the density of inserts varying from one layer to another, therefore varying the number (Z) resulting from the hardening device throughout its thickness according to a predefined law.

6. 发明申请

WO1985004523A1 CONDUCTIVE, PROTECTIVE LAYER FOR MULTILAYER METALLIZATION 审中-公开
标题翻译：导电性，多层金属保护层
公开(公告)号：WO1985004523A1
公开(公告)日：1985-10-10
申请号：PCT/US1985000354
申请日：1985-03-04
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ADVANCED MICRO DEVICES, INC. , BORODOVSKY, Yan, A.
IPC分类号： H01L23/54
CPC分类号： H01L21/76886 , H01L23/53271 , H01L2924/0002 , Y10S438/945 , Y10S438/968 , Y10S438/97 , H01L2924/00
摘要： An integrated circuit structure, and method of making the structure, wherein at least one metallization layer (10) is coated with a conductive indium arsenide layer (12) during production of the structure and an upper metallization layer (40) subsequently is applied to the structure wherein at least a portion of the subsequent metallization layer (40) is in ohmic contact with the conductive indium arsenide layer (12) whereby the lower metallization layer is protected by the intervening indium arsenide layer (12) during subsequent removal of the upper metallization layer if subsequent reworking of the structure becomes necessary. The use of the indium arsenide layer (12) over a metallization layer (10) further enhances the construction process by the use of its antireflective properties during patterning of a photoresist applied over the indium arsenide layer.
摘要翻译：一种集成电路结构以及制造该结构的方法，其中至少一个金属化层（10）在该结构的制造期间涂覆有导电的砷化铟层（12），并且上部金属化层（40）随后被施加到结构，其中随后的金属化层（40）的至少一部分与导电砷化铟层（12）欧姆接触，由此下一金属化层在随后的去除上金属化层期间被中间的砷化铟层（12）保护如果需要对结构进行后续的返工。在金属化层（10）上使用砷化铟层（12）通过在对砷化铟层施加的光刻胶进行图案化期间通过使用其抗反射性能来进一步增强施工工艺。

7. 发明授权

US6093967A Self-aligned silicide contacts formed from deposited silicon 失效
标题翻译：由沉积硅形成的自对准硅化物触点
公开(公告)号：US6093967A
公开(公告)日：2000-07-25
申请号：US992573
申请日：1997-12-17
申请人： Yowjuang W. Liu , Mark S. Chang , Michael K. Templeton
发明人： Yowjuang W. Liu , Mark S. Chang , Michael K. Templeton
IPC分类号： H01L21/285 , H01L23/54 , H01L21/441
CPC分类号： H01L21/28518
摘要： Self-aligned silicide contacts having a height that is at least about equal to the gate height are formed by depositing silicon over active regions of the substrate, depositing a refractory metal over the silicon, and heating the silicon and the refractory metal. The deposited silicon may be amorphous silicon in which case the deposition temperature can be as low as 580.degree. C. If polysilicon is deposited, the deposition temperature has to be at least 620.degree. C.
摘要翻译：通过在衬底的有源区上沉积硅，在硅上沉积难熔金属，并加热硅和难熔金属，形成具有至少约等于栅极高度的高度的自对准硅化物触点。沉积的硅可以是非晶硅，在这种情况下，沉积温度可以低至580℃。如果沉积多晶硅，则沉积温度必须至少为620℃。

8. 发明授权

US5834827A Thin film semiconductor device, fabrication method thereof, electronic device and its fabrication method 失效
标题翻译：薄膜半导体器件及其制造方法，电子器件及其制造方法
公开(公告)号：US5834827A
公开(公告)日：1998-11-10
申请号：US748835
申请日：1996-11-14
申请人： Mitsutoshi Miyasaka , Kiyofumi Kitawada , Minoru Matsuo , Seiichiro Higashi , Tokuroh Ozawa , Satoshi Takenaka , Yojiro Matsueda , Takashi Nakazawa , Hiroyuki Ohshima , Satoshi Inoue
发明人： Mitsutoshi Miyasaka , Kiyofumi Kitawada , Minoru Matsuo , Seiichiro Higashi , Tokuroh Ozawa , Satoshi Takenaka , Yojiro Matsueda , Takashi Nakazawa , Hiroyuki Ohshima , Satoshi Inoue
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/786 , H01L23/54
CPC分类号： H01L29/66757 , H01L21/28079 , H01L29/4908 , H01L29/78675
摘要： Electronic devices are provided with electrically conductive interconnections which are formed on the insulator material. Such electronic devices include, for example, thin film semiconductor devices (TFT), metal-insulator-metallic type non-wiring elements (MIM), solar cells, Large Scale Integration devices (LSI) or printed-wiring boards. At least a part of the electrically conductive interconnections are made of .alpha.-structure tantalum (Ta) which contains hydrogen. The .alpha.-structure tantalum does not have cubical crystals in its crystal system, but rather has body-centered cubes (bcc). The resistivity of the .alpha.-structure tantalum is from about 20 .mu..OMEGA. centimeters to about 60 .mu..OMEGA. centimeters. When hydrogen is included within this .alpha.-structure tantalum film, small amounts of nitrogen may be contained along with the hydrogen in the film. When a semiconductor layer is directly formed on the lower conductive layer, the upper conductive layer contains, as a primary component, the hydrogen contained .alpha.-structure tantalum.
摘要翻译：电子设备设置有形成在绝缘体材料上的导电互连。这种电子器件包括例如薄膜半导体器件（TFT），金属 - 绝缘体 - 金属型非布线元件（MIM），太阳能电池，大规模集成器件（LSI）或印刷电路板。至少一部分导电互连由含有氢的α结构钽（Ta）制成。 α结构钽在其晶体系统中不具有立方晶体，而是具有以体积为中心的立方体（bcc）。 α结构钽的电阻率为约20微米欧米算至约60微米欧米加厘米。当在该α结构钽膜中包含氢时，可能含有少量的氮以及膜中的氢。当半导体层直接形成在下导电层上时，上导电层含有含氢的α结构钽作为主要成分。

9. 发明授权

US5616959A Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators 失效
标题翻译：具有嵌入式低介电常数绝缘体的平面化多级互连方案
公开(公告)号：US5616959A
公开(公告)日：1997-04-01
申请号：US473458
申请日：1995-06-07
申请人： Shin-Puu Jeng
发明人： Shin-Puu Jeng
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L29/28 , H01L23/54
CPC分类号： H01L23/5222 , H01L21/76801 , H01L21/76834 , H01L23/5329 , H01L21/76837 , H01L2924/0002 , H01L2924/12044
摘要： A multi-level interconnect structure and method. A first plurality of interconnect lines (14) is located on an insulator layer (12) of semiconductor body (10). A first layer of low dielectric constant material (20), such as an organic polymer, fills an area between the first plurality of interconnect lines (14a-c) . The first layer of low dielectric constant material (20) has a height not greater than a height of the first plurality of interconnect lines (14). A first layer of silicon dioxide (18) covers the first layer of low dielectric constant material (20) and the first plurality of interconnect lines (14).
摘要翻译：多级互连结构和方法。第一多个互连线（14）位于半导体本体（10）的绝缘体层（12）上。诸如有机聚合物的第一层低介电常数材料（20）填充第一多个互连线（14a-c）之间的区域。第一层低介电常数材料（20）具有不大于第一多个互连线（14）的高度的高度。第一层二氧化硅（18）覆盖第一层低介电常数材料（20）和第一多个互连线（14）。

10. 发明授权

US4809055A Semiconductor device having an electrode and a method of manufacturing the same 失效
标题翻译：具有电极的半导体装置及其制造方法
公开(公告)号：US4809055A
公开(公告)日：1989-02-28
申请号：US191747
申请日：1988-05-05
申请人： Masaru Ishibashi , Takeshi Tsubata , Kazumi Sasaki
发明人： Masaru Ishibashi , Takeshi Tsubata , Kazumi Sasaki
IPC分类号： H01L29/73 , H01L21/28 , H01L21/331 , H01L23/485 , H01L23/532 , H01L29/732 , H01L23/54 , H01L23/14
CPC分类号： H01L23/53242 , H01L23/4855 , H01L2924/0002
摘要： An SiO.sub.2 insulating layer is formed on an Si substrate, and an Si.sub.3 N.sub.4 insulating layer is formed on the SiO.sub.2 layer. A notch is formed in the Si.sub.3 N.sub.4 layer using a resist film as a mask. The SiO.sub.2 layer is etched using the Si.sub.3 N.sub.4 layer as a mask, thereby forming an opening larger than the notch cut in the SiO.sub.2 layer. As a result, the Si.sub.3 N.sub.4 layer extends over the opening in an overhanging manner. When As.sup.+ ions are implanted in the periphery of the notch of the Si.sub.3 N.sub.4 layer, the ion-implanted portion of the Si.sub.3 N.sub.4 layer is arcuated toward the base region. When a metal such as Ti is deposited on the arcuated portion, the metal is also deposited on the arcuated portion and the portion of the emitter region matching with the notch, thereby forming an emitter electrode portion.
摘要翻译：在Si衬底上形成SiO 2绝缘层，在SiO 2层上形成Si 3 N 4绝缘层。使用抗蚀剂膜作为掩模在Si 3 N 4层中形成切口。使用Si 3 N 4层作为掩模蚀刻SiO 2层，从而形成比在SiO 2层中切割的切口大的开口。结果，Si 3 N 4层以突出的方式在开口上延伸。当As +离子注入到Si 3 N 4层的凹口的周围时，Si 3 N 4层的离子注入部分朝向基极区域弧形化。当诸如Ti的金属沉积在弧形部分上时，金属也沉积在弧形部分上，并且发射极区域的部分与凹口匹配，从而形成发射极电极部分。

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