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1. 发明授权

US4471373A Semiconductor integrated circuit device with memory MISFETS and thin and thick gate insulator MISFETS 失效
标题翻译：具有存储器MISFETS和薄和厚栅极绝缘体MISFET的半导体集成电路器件
公开(公告)号：US4471373A
公开(公告)日：1984-09-11
申请号：US223140
申请日：1981-01-07
申请人： Shinji Shimizu , Kazuhiro Komori , Yasunobu Kosa , June Sugiura
发明人： Shinji Shimizu , Kazuhiro Komori , Yasunobu Kosa , June Sugiura
IPC分类号： H01L21/28 , H01L21/32 , H01L21/82 , H01L21/8247 , H01L27/105 , H01L29/423 , H01L29/788 , H01L29/792 , H01L27/02 , H01L29/78
CPC分类号： H01L27/11526 , H01L21/28273 , H01L21/32 , H01L21/82 , H01L27/105 , H01L27/11546 , H01L29/42364
摘要： A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.
摘要翻译：一种半导体集成电路器件及其制造方法，其中在半导体衬底的表面上形成有两层栅电极结构的MIS型存储晶体管，以及具有相对较薄的低电压的MIS型晶体管在存储晶体管的周围形成栅氧化膜和具有较厚栅极氧化膜的高压用MIS型晶体管。

2. 发明授权

US4451904A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4451904A
公开(公告)日：1984-05-29
申请号：US228086
申请日：1981-01-26
申请人： June Sugiura , Yasunobu Kosa , Kazuhiro Komori , Ken Uchida , Shinji Shimizu
发明人： June Sugiura , Yasunobu Kosa , Kazuhiro Komori , Ken Uchida , Shinji Shimizu
IPC分类号： H01L27/112 , G11C5/02 , G11C16/04 , G11C17/00 , H01L21/8246 , H01L21/8247 , H01L23/522 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： G11C5/02 , H01L23/522 , H01L27/115 , H01L2924/0002
摘要： A semiconductor memory device includes a number of conductive layers for bit and selection lines alternately juxtaposed on the surface of a semiconductor substrate beneath a field insulating layer, with a number of MOS type memory cells arranged between the conductive layers for the bit and selection lines.
摘要翻译：半导体存储器件包括用于位和选择线的多个导电层，其交替并置在半导体衬底的场绝缘层下的表面，多个MOS型存储单元布置在用于位和选择线的导电层之间。

3. 发明授权

US4651406A Forming memory transistors with varying gate oxide thicknesses 失效
标题翻译：形成具有不同栅极氧化物厚度的存储晶体管
公开(公告)号：US4651406A
公开(公告)日：1987-03-24
申请号：US873056
申请日：1986-06-04
申请人： Shinji Shimizu , Kazuhiro Komori , Yasunobu Kosa , June Sugiura
发明人： Shinji Shimizu , Kazuhiro Komori , Yasunobu Kosa , June Sugiura
IPC分类号： H01L21/28 , H01L21/32 , H01L21/82 , H01L21/8247 , H01L27/105 , H01L29/423 , H01L29/788 , H01L29/792 , H01L21/425
CPC分类号： H01L27/11526 , H01L21/28273 , H01L21/32 , H01L21/82 , H01L27/105 , H01L27/11546 , H01L29/42364
摘要： A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.
摘要翻译：一种半导体集成电路器件及其制造方法，其中在半导体衬底的表面上形成有两层栅电极结构的MIS型存储晶体管，以及具有相对较薄的低电压的MIS型晶体管在存储晶体管的周围形成栅氧化膜和具有较厚栅极氧化膜的高压用MIS型晶体管。

4. 发明授权

US4426764A Semiconductor memory device with peripheral circuits 失效
标题翻译：具有外围电路的半导体存储器件
公开(公告)号：US4426764A
公开(公告)日：1984-01-24
申请号：US241539
申请日：1981-03-09
申请人： Yasunobu Kosa , Shinji Shimizu
发明人： Yasunobu Kosa , Shinji Shimizu
IPC分类号： H01L21/8247 , H01L21/28 , H01L29/51 , H01L29/788 , H01L29/792 , H01L21/22
CPC分类号： H01L21/28211 , H01L21/28273 , H01L29/511 , H01L29/7886
摘要： A semiconductor memory device and a method of manufacturing the device wherein a field insulation is formed in a surface of a semiconductor body except for the source, drain and channel regions, a first floating gate is self-aligned to the channel region, a second gate insulated from the first floating gate covers the first floating gate and the first insulator having a width substantially same as the length of the channel region between the source and the drain regions.
摘要翻译：一种半导体存储器件及其制造方法，其中除了源极，漏极和沟道区之外，在半导体本体的表面形成有场绝缘，第一浮栅与沟道区自对准，第二栅极与第一浮动栅极绝缘覆盖第一浮动栅极和第一绝缘体，其宽度基本上与源极和漏极区域之间的沟道区域的长度相同。

5. 发明授权

US4926222A Semiconductor memory device and a method of manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US4926222A
公开(公告)日：1990-05-15
申请号：US545767
申请日：1983-10-26
申请人： Yasunobu Kosa , Shinji Shimizu
发明人： Yasunobu Kosa , Shinji Shimizu
IPC分类号： H01L21/8247 , H01L21/28 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28211 , H01L21/28273 , H01L29/511 , H01L29/7886
摘要： A semiconductor memory device and a method of manufacturing the device wherein a field insulation is formed in a surface of a semiconductor body except for the source, drain and channel regions, a first floating gate is self-aligned to the channel region, a second gate insulated from the first floating gate covers the first floating gate and the first insulator having a width substantially same as the length of the channel region between the source and the drain regions.

6. 发明授权

US08537300B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US08537300B2
公开(公告)日：2013-09-17
申请号：US12700760
申请日：2010-02-05
申请人： Yoshio Toriyama , Shinji Shimizu , Akio Tezuka , Masafumi Nagaoka
发明人： Yoshio Toriyama , Shinji Shimizu , Akio Tezuka , Masafumi Nagaoka
IPC分类号： G02F1/1333
CPC分类号： G02F1/133608
摘要： A display device includes a display panel unit and a backlight unit which radiates light toward the display panel. The display panel unit includes a display panel on an upper surface of a box-shaped panel housing which has first projecting portions on side walls of the housing. The backlight unit incorporates a light source in a bottom portion of a box-shaped light source housing which has second projecting portions on side walls of the light source housing. By bringing the first projecting portions and second projecting portions into contact with each other, a distance between the light source of the backlight unit and the display panel can be held. Further, by forming third projecting portions which project further than the first projecting portions on the panel housing, handling of the display panel unit is facilitated.
摘要翻译：显示装置包括向显示面板照射光的显示面板单元和背光单元。显示面板单元包括在盒形面板壳体的上表面上的显示面板，其在壳体的侧壁上具有第一突出部分。背光单元在光源壳体的侧壁上具有在盒形光源壳体的底部中的第二突出部分的光源。通过使第一突出部和第二突出部彼此接触，可以保持背光单元的光源与显示面板之间的距离。此外，通过形成比面板壳体上的第一突出部更远的第三突出部，便于显示面板单元的处理。

7. 发明授权

US06503685B1 Heat sensitive composition, original plate using the same for lithographic printing plate, and process for preparing printing plate 失效
标题翻译：热敏组合物，用于平版印刷版的原版，以及制备印版的方法
公开(公告)号：US06503685B1
公开(公告)日：2003-01-07
申请号：US09711082
申请日：2000-11-14
申请人： Shinji Shimizu , Yasuyuki Watanabe , Yasuhiko Kojima , Koji Oe , Nansei Tasiro
发明人： Shinji Shimizu , Yasuyuki Watanabe , Yasuhiko Kojima , Koji Oe , Nansei Tasiro
IPC分类号： G03C173
CPC分类号： G03F7/202 , B41C1/1025 , B41C2210/02 , B41C2210/04 , B41C2210/06 , B41C2210/22 , B41C2210/24 , B41C2210/262 , B41M5/26 , B41M5/368 , C08J3/07 , C08J3/12
摘要： A heat-sensitive composition is disclosed which includes a substance which absorbs light and generates heat, an anionic self water-dispersible resin particle having an acid value of 10 to 300 and an average particle diameter of 0.005 to 15 &mgr;m, and a fluorine base surfactant. An original plate for a lithographic printing plate is disclosed which includes an ordinary negative- or positive-type PS plate having coated thereon the heat-sensitive composition. The original plate is image-wise exposed with high energy density light based on digital image information from a computer, subjected to first development with an aqueous alkali solution, flood exposure with active light, a second development with a developer for a negative or a positive, and post-treatment to obtain a printing plate.
摘要翻译：公开了一种热敏性组合物，其包含吸收光并产生热的物质，酸值为10〜300，平均粒径为0.005〜15μm的阴离子型自分散水性树脂粒子，氟基表面活性剂。公开了一种用于平版印刷版的原版，其包括在其上涂覆有热敏组合物的普通负型或正型PS板。基于来自计算机的数字图像信息，用碱性水溶液进行第一次显影，用活性光进行暴露曝光，用显影剂进行负面或阳性的第二次显影，将原始平板以高能量密度的光图像曝光，并进行后处理以获得印版。

8. 发明授权

US06284174B1 Melt spinning pack and synthetic fiber manufacturing method 失效
标题翻译：熔纺丝包和合成纤维制造方法
公开(公告)号：US06284174B1
公开(公告)日：2001-09-04
申请号：US09424954
申请日：1999-12-06
申请人： Kunihiko Ueda , Toshio Nishitani , Hiroki Furuta , Teruaki Saijo , Kanji Saito , Hiroshi Kato , Hiroshi Ohtani , Shinji Shimizu , Koji Hashimoto
发明人： Kunihiko Ueda , Toshio Nishitani , Hiroki Furuta , Teruaki Saijo , Kanji Saito , Hiroshi Kato , Hiroshi Ohtani , Shinji Shimizu , Koji Hashimoto
IPC分类号： D01D110
CPC分类号： D01D4/00 , D01D4/02 , D01D4/06
摘要： A melt spinning pack, including a pack case, a spinneret having many spinning holes positioned at the bottom of the case, a pack cap having a polymer introducing hole at the center positioned at the top of the case, and a flow arranging plate having many flow arranging holes with restricted portions reduced in cross sectional area compared to the inlets of the holes positioned between the spinneret and the pack cap, satisfying the requirement that the contraction percentage R be 50% or less, respectively contained in the case.
摘要翻译：一种熔融纺丝组件，包括一个包装盒，一个具有位于壳体底部的许多纺丝孔的喷丝头，一个在壳体顶部位于中心位置处具有聚合物引入孔的包装盖，以及具有许多与位于喷丝头和包装盖之间的孔的入口相比，具有限制部分的横截面积减小的流动分配孔满足分别包含在壳体中的收缩百分比R为50％或更小的要求。

9. 发明授权

US06281071B1 Method of producing semiconductor integrated circuit device having switching MISFET and capacitor element including wiring therefor and method of producing such wiring 失效
标题翻译：具有开关MISFET和包括其布线的电容器元件的半导体集成电路器件的制造方法以及制造这种布线的方法
公开(公告)号：US06281071B1
公开(公告)日：2001-08-28
申请号：US09317999
申请日：1999-05-25
申请人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
发明人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
IPC分类号： H01L218242
CPC分类号： H01L27/105 , H01L27/10808
摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it. In a fifth aspect, the capacitor dielectric film is a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure. In sixth and seventh aspects, wiring is provided.
摘要翻译：公开了一种具有开关MISFET的半导体集成电路器件和形成在诸如DRAM的半导体衬底之上的电容器元件。在本发明的第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。在第二方面，Y选择信号线与电容器元件的下电极层重叠。在第三方面中，通过用于沟道阻挡区域的杂质的扩散，形成至少在电容器元件连接的开关MISFET的半导体区域下方的势垒层。在第四方面中，电容器元件的电介质膜与其上的电容器电极层共同扩展。在第五方面中，电容器电介质膜是其上具有氧化硅层的氮化硅膜，通过在高压下氧化氮化硅的表面层而形成氧化硅层。在第六和第七方面中，提供了布线。

10. 发明授权

US5753550A Semiconductor integrated circuit device having switching MISFET and capacitor element and method of producing the same, including wiring therefor and method of producing such wiring 失效
标题翻译：具有开关MISFET和电容器元件的半导体集成电路器件及其制造方法，包括其布线及其制造方法
公开(公告)号：US5753550A
公开(公告)日：1998-05-19
申请号：US620867
申请日：1996-03-25
申请人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
发明人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108
CPC分类号： H01L27/105 , H01L27/10808
摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In other aspects, a Y-select signal line overlaps the lower electrode layer of the capacitor element; a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region; the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it, the capacitor dielectric film being a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure; an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide, is used as the protective layer for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.
摘要翻译：公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。在第一方面中，电容器元件所连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。在其他方面，Y选择信号线与电容器元件的下电极层重叠; 至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成; 电容器元件的电介质膜与其上的电容器电极层共同扩展，电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过氧化氮化硅的表面层而形成在高压下通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物用作用于包含添加元素（例如Cu）以防止迁移的铝布线的保护层。

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