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1. 发明授权

US07804129B2 Recessed gate electrode MOS transistor and method for fabricating the same 有权
标题翻译：嵌入式栅电极MOS晶体管及其制造方法
公开(公告)号：US07804129B2
公开(公告)日：2010-09-28
申请号：US11157999
申请日：2005-06-21
申请人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
发明人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
IPC分类号： H01L29/76 , H01L21/3205
CPC分类号： H01L29/66795 , H01L27/10876 , H01L27/10879 , H01L29/7853
摘要： Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.
摘要翻译：公开了一种晶体管及其制造方法，其能够增加晶体管的阈值电压和驱动电流。该方法包括以下步骤：在硅衬底上形成第一蚀刻掩模，通过蚀刻暴露的隔离区域形成沟槽，在沟槽中形成第一绝缘层和第一蚀刻掩模，在第一绝缘层上形成第二绝缘层去除所述第二绝缘层和所述第一绝缘层直到所述第一蚀刻掩模被暴露，在所述隔离区域上形成沟槽型隔离层，在所述硅衬底的整个表面上形成第二蚀刻掩模，蚀刻所述暴露的沟道区域，对所得基板结构进行蚀刻处理，以及在所述凹部中形成栅极。

2. 发明申请

US20060273381A1 Transistor and method for fabricating the same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US20060273381A1
公开(公告)日：2006-12-07
申请号：US11157999
申请日：2005-06-21
申请人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
发明人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
IPC分类号： H01L29/94
CPC分类号： H01L29/66795 , H01L27/10876 , H01L27/10879 , H01L29/7853
摘要： Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.
摘要翻译：公开了一种晶体管及其制造方法，其能够增加晶体管的阈值电压和驱动电流。该方法包括以下步骤：在硅衬底上形成第一蚀刻掩模，通过蚀刻暴露的隔离区域形成沟槽，在沟槽中形成第一绝缘层和第一蚀刻掩模，在第一绝缘层上形成第二绝缘层去除所述第二绝缘层和所述第一绝缘层直到所述第一蚀刻掩模被暴露，在所述隔离区域上形成沟槽型隔离层，在所述硅衬底的整个表面上形成第二蚀刻掩模，蚀刻所述暴露的沟道区域，对所得基板结构进行蚀刻处理，以及在所述凹部中形成栅极。

3. 发明授权

US08058141B2 Recessed gate electrode MOS transistor and method for fabricating the same 有权
标题翻译：嵌入式栅电极MOS晶体管及其制造方法
公开(公告)号：US08058141B2
公开(公告)日：2011-11-15
申请号：US12861111
申请日：2010-08-23
申请人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
发明人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
IPC分类号： H01L21/76
CPC分类号： H01L29/66795 , H01L27/10876 , H01L27/10879 , H01L29/7853
摘要： Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.
摘要翻译：公开了一种晶体管及其制造方法，其能够增加晶体管的阈值电压和驱动电流。该方法包括以下步骤：在硅衬底上形成第一蚀刻掩模，通过蚀刻暴露的隔离区域形成沟槽，在沟槽中形成第一绝缘层和第一蚀刻掩模，在第一绝缘层上形成第二绝缘层去除所述第二绝缘层和所述第一绝缘层直到所述第一蚀刻掩模被暴露，在所述隔离区域上形成沟槽型隔离层，在所述硅衬底的整个表面上形成第二蚀刻掩模，蚀刻所述暴露的沟道区域，对所得基板结构进行蚀刻处理，以及在所述凹部中形成栅极。

4. 发明授权

US07601583B2 Transistor structure of memory device and method for fabricating the same 有权
标题翻译：存储器件的晶体管结构及其制造方法
公开(公告)号：US07601583B2
公开(公告)日：2009-10-13
申请号：US11962100
申请日：2007-12-21
申请人： Se Aug Jang , Yong Soo Kim , Jae Geun Oh , Jae Sung Rohh , Hyun Chul Sohn
发明人： Se Aug Jang , Yong Soo Kim , Jae Geun Oh , Jae Sung Rohh , Hyun Chul Sohn
IPC分类号： H01L29/72
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/66621 , H01L29/66795 , H01L29/7851
摘要： A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.
摘要翻译：存储器件包括从半导体衬底突出的有源区。在活动区域中形成凹部。在半导体衬底上形成场氧化物层。栅极电极延伸穿过有源区域同时与凹部重叠。栅极绝缘层介于栅电极和有源区之间。源极和漏极区域形成在有源区域中。如果上述晶体管结构沿着源极 - 漏极线分段而限定了凹陷的晶体管结构，并且如果沿着栅极线分段则限定了Fin晶体管结构。晶体管结构确保足够的数据保持时间，并且在降低阈值电压的反偏压依赖性的同时提高电流驱动能力。

5. 发明申请

US20080096355A1 TRANSISTOR STRUCTURE OF MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：存储器件的晶体管结构及其制造方法
公开(公告)号：US20080096355A1
公开(公告)日：2008-04-24
申请号：US11962100
申请日：2007-12-21
申请人： Se Aug Jang , Yong Soo Kim , Jae Geun Oh , Jae Roh , Hyun Chul Sohn
发明人： Se Aug Jang , Yong Soo Kim , Jae Geun Oh , Jae Roh , Hyun Chul Sohn
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/66621 , H01L29/66795 , H01L29/7851
摘要： A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.
摘要翻译：存储器件包括从半导体衬底突出的有源区。在活动区域中形成凹部。在半导体衬底上形成场氧化物层。栅极电极延伸穿过有源区域同时与凹部重叠。栅极绝缘层介于栅电极和有源区之间。源极和漏极区域形成在有源区域中。如果上述晶体管结构沿着源极 - 漏极线分段而限定了凹陷的晶体管结构，并且如果沿着栅极线分段则限定了Fin晶体管结构。晶体管结构确保足够的数据保持时间，并且在降低阈值电压的反偏压依赖性的同时提高电流驱动能力。

6. 发明授权

US06537901B2 Method of manufacturing a transistor in a semiconductor device 失效
公开(公告)号：US06537901B2
公开(公告)日：2003-03-25
申请号：US09887511
申请日：2001-06-25
申请人： Tae Ho Cha , Se Aug Jang , Tae Kyun Kim , Dea Gyu Park , In Seok Yeo , Jin Won Park
发明人： Tae Ho Cha , Se Aug Jang , Tae Kyun Kim , Dea Gyu Park , In Seok Yeo , Jin Won Park
IPC分类号： H01L213205
CPC分类号： C23C16/34 , C23C14/0641 , H01L21/28079 , H01L21/28088 , H01L21/2855 , H01L21/28556 , H01L21/28562 , H01L21/28568 , H01L21/823828 , H01L29/4958 , H01L29/4966
摘要： There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention forms a Ta film or a TaNx film at a low temperature or forms a first TaNx film in which the composition(x) of nitrogen is 0.45˜0.55, on a gate insulating film in a NMOS region, so that the work function becomes 4.0˜4.4 eV, and also forms a Ta film or a TaNx film at a high temperature or forms a second TaNx film in which the composition(x) of nitrogen is 0.6˜1.4 is formed, on a gate insulating film in a PMOS region, so that the work function becomes 4.8˜5.2 eV. Thus, the present invention can lower the threshold voltage by implementing a surface channel CMOS device both in the NMOS region and the PMOS region.

7. 发明授权

US06506676B2 Method of manufacturing semiconductor devices with titanium aluminum nitride work function 有权
标题翻译：制造具有钛氮化铝功能的半导体器件的方法
公开(公告)号：US06506676B2
公开(公告)日：2003-01-14
申请号：US10033509
申请日：2001-12-27
申请人： Dae Gyu Park , Tae Ho Cha , Se Aug Jang , Heung Jae Cho , Tae Kyun Kim , Kwan Yong Lim , In Seok Yeo , Jin Won Park
发明人： Dae Gyu Park , Tae Ho Cha , Se Aug Jang , Heung Jae Cho , Tae Kyun Kim , Kwan Yong Lim , In Seok Yeo , Jin Won Park
IPC分类号： H01L2144
CPC分类号： H01L21/28194 , C23C14/048 , C23C16/34 , H01L21/28556 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/518
摘要： A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.
摘要翻译：制造半导体器件的方法在制造金属栅极的过程中形成表面沟道CMOSFET。该方法在nMOS区域的栅极绝缘膜上形成具有约4.2至约4.3eV的功函数值的（TixAly）1-zNz膜（其中z范围为约0.0至约0.2），（TixAly）1 -zNz膜（其中z范围为约0.3至约0.6），在pMOS区域中的栅极绝缘膜上具有约4.8至约5.0eV的功函数值，从而在nMOS区域和 pMOS区域。因此，阈值电压降低。

8. 发明授权

US06451639B1 Method for forming a gate in a semiconductor device 失效
标题翻译：在半导体器件中形成栅极的方法
公开(公告)号：US06451639B1
公开(公告)日：2002-09-17
申请号：US10036279
申请日：2001-11-07
申请人： Se Aug Jang , Tae Kyun Kim , Jae Young Kim , In Seok Yeo
发明人： Se Aug Jang , Tae Kyun Kim , Jae Young Kim , In Seok Yeo
IPC分类号： H01L21338
CPC分类号： H01L21/823842
摘要： A method of forming a semiconductor device gate including the steps of forming a dummy gate insulating layer on a semiconductor substrate having an isolating field oxide layer, successively depositing a dummy gate silicon layer and a hard mask layer on the dummy gate insulating layer, forming a hard mask layer and patterning the dummy gate silicon layer using the mask pattern as an etch barrier, forming a thermal oxide layer at both sidewalls of the dummy gate silicon layer by thermal oxidation on the resultant structure, forming spacers at both sidewalls of the dummy gate silicon layer, depositing an insulating interlayer on the resultant structure, polishing the insulating interlayer to expose the dummy gate silicon layer, forming a damascene structure by removing the dummy gate silicon and insulating layers, depositing a gate insulating layer and a gate metal layer on an entire surface of the semiconductor substrate having the damascene structure, and polishing the gate metal and insulating layers, thereby preventing the undercut at the bottom corners of a damascene groove.
摘要翻译：一种形成半导体器件栅极的方法，包括以下步骤：在具有隔离场氧化物层的半导体衬底上形成伪栅极绝缘层，在虚拟栅绝缘层上依次沉积伪栅极硅层和硬掩模层，形成硬掩模层，并且使用掩模图案作为蚀刻阻挡层来图案化伪栅极硅层，在所得结构上通过热氧化在所述伪栅极硅层的两个侧壁处形成热氧化物层，在所述伪栅极的两个侧壁处形成间隔物在所得到的结构上沉积绝缘中间层，抛光绝缘中间层以露出伪栅极硅层，通过去除伪栅极硅和绝缘层形成镶嵌结构，在栅极上沉积栅极绝缘层和栅极金属层半导体衬底的整个表面具有镶嵌结构，并且对栅极金属进行研磨从而防止镶嵌槽的底角处的底切。

9. 发明授权

US06514827B2 Method for fabricating a dual metal gate for a semiconductor device 失效
标题翻译：半导体器件的双金属栅极的制造方法
公开(公告)号：US06514827B2
公开(公告)日：2003-02-04
申请号：US10034529
申请日：2001-12-28
申请人： Tae Kyun Kim , Se Aug Jang , Tae Ho Cha , In Seok Yeo
发明人： Tae Kyun Kim , Se Aug Jang , Tae Ho Cha , In Seok Yeo
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/823842
摘要： A method for fabricating a dual metal gate structure for a semiconductor device including deposition of a semiconductor substrate having PMOS and NMOS regions, a first gate having a first insulating layer and a first metal layer is formed in a first region. The first region is either the PMOS or NMOS region, and the remaining region becomes a second region. A dummy gate is formed in the second region. A spacer and a source/drain region are formed for each of the first and dummy gates. The dummy gate, however, is removed to expose a portion of the substrate in the second region. A second gate constructed of a second gate insulating layer and a second metal layer is then formed on the exposed portion of the substrate in the second region.
摘要翻译：一种用于制造半导体器件的双金属栅极结构的方法，包括具有PMOS和NMOS区域的半导体衬底的沉积，在第一区域中形成具有第一绝缘层和第一金属层的第一栅极。第一区域是PMOS或NMOS区域，其余区域成为第二区域。在第二区域中形成伪栅极。为第一和虚拟栅极中的每一个形成间隔物和源极/漏极区域。然而，去除伪栅极以暴露第二区域中的衬底的一部分。然后在第二区域中的衬底的暴露部分上形成由第二栅极绝缘层和第二金属层构成的第二栅极。

10. 发明授权

US06468914B1 Method of forming gate electrode in semiconductor device 失效
标题翻译：在半导体器件中形成栅电极的方法
公开(公告)号：US06468914B1
公开(公告)日：2002-10-22
申请号：US09472541
申请日：1999-12-27
申请人： Se Aug Jang , In Seok Yeo
发明人： Se Aug Jang , In Seok Yeo
IPC分类号： H01L2144
CPC分类号： H01L29/6656 , H01L21/28061 , H01L21/28247 , H01L29/6659
摘要： A method of forming a gate electrode in a semiconductor device which can prevent abnormal oxidation of a titanium silicide layer when performing gate re-oxidation process after a gate electrode having a stacked structure of a doped polysilicon layer and the titanium silicide layer.
摘要翻译：一种在半导体器件中形成栅电极的方法，其可以在具有掺杂多晶硅层和硅化钛层的堆叠结构的栅极之后执行栅极再氧化处理时防止硅化钛层的异常氧化。

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