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1. 发明授权

US07813163B2 Single-ended read and differential write scheme 失效
标题翻译：单端读和差分写入方案
公开(公告)号：US07813163B2
公开(公告)日：2010-10-12
申请号：US12190680
申请日：2008-08-13
申请人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
发明人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.
摘要翻译：提供了读取和写入至少一个静态存储单元的方法，所述单元包括交叉耦合的反相器对和两个通过器件，其中所述方法的特征在于，在只读选择两个通过器件中的一个的同时，对于写入，选择了传递设备。此外，描述了读取和写入至少一个静态存储器单元的电路，所述单元包括交叉耦合的反相器对和两个通过器件。所述电路的特征在于，对于单元的每个通过器件，单个字线与特定通过器件的栅极连接，其中两个字线被选择用于写入，并且单个字线被选择用于读取。

2. 发明申请

US20090059688A1 Single-ended read and differential write scheme 失效
标题翻译：单端读和差分写入方案
公开(公告)号：US20090059688A1
公开(公告)日：2009-03-05
申请号：US12190680
申请日：2008-08-13
申请人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
发明人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C11/413
摘要： A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.
摘要翻译：提供了读取和写入至少一个静态存储单元的方法，所述单元包括交叉耦合的反相器对和两个通过器件，其中所述方法的特征在于，在只读选择两个通过器件中的一个的同时，对于写入，选择了传递设备。此外，描述了读取和写入至少一个静态存储器单元的电路，所述单元包括交叉耦合的反相器对和两个通过器件。所述电路的特征在于，对于单元的每个通过器件，单个字线与特定通过器件的栅极连接，其中两个字线被选择用于写入，并且单个字线被选择用于读取。

3. 发明授权

US07289370B2 Methods and apparatus for accessing memory 有权
公开(公告)号：US07289370B2
公开(公告)日：2007-10-30
申请号：US11186606
申请日：2005-07-21
申请人： Chad Allen Adams , Anthony Gus Aipperspach , Juergen Pille , Otto Wagner
发明人： Chad Allen Adams , Anthony Gus Aipperspach , Juergen Pille , Otto Wagner
IPC分类号： G11C16/04
CPC分类号： G11C11/413 , G11C7/06 , G11C7/1006 , G11C7/12
摘要： In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.

4. 发明申请

US20080080259A1 6 Transistor Memory Circuit Pair Supporting Simultaneous Read/Write and Method Therefore 审中-公开
标题翻译： 6晶体管存储电路对支持同时读/写和方法因此
公开(公告)号：US20080080259A1
公开(公告)日：2008-04-03
申请号：US11862235
申请日：2007-09-27
申请人： Stefan Buettner , Juergen Pille , Otto Wagner , Dieter Wendel
发明人： Stefan Buettner , Juergen Pille , Otto Wagner , Dieter Wendel
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/18
摘要： A method and memory circuit comprising a plurality of cells accessible by word lines and bit lines is described, wherein each cell includes a group of six transistors adapted to both store a bit inserted into the cell during a write operation and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell, wherein the word lines and bit lines of the memory are divided into sections assigned to groups of equal numbers of cells, wherein said sections are individually accessible for read or write operations such that one cell of a group can be read simultaneously while writing another cell of the group.
摘要翻译：描述了包括由字线和位线可访问的多个单元的方法和存储器电路，其中每个单元包括一组六个晶体管，其适于在写操作期间存储插入到单元中的位，并且影响在在耦合到该单元的位线上读取操作，使得受影响的信号与存储在单元中的位的值相匹配，其中存储器的字线和位线被分成分配给相同数量的单元的组，其中所述部分可单独访问用于读取或写入操作，使得可以同时读取组中的一个单元同时写入该组的另一个单元。

5. 发明申请

US20070019461A1 Methods and apparatus for accessing memory 有权
标题翻译：访问内存的方法和设备
公开(公告)号：US20070019461A1
公开(公告)日：2007-01-25
申请号：US11186606
申请日：2005-07-21
申请人： Chad Adams , Anthony Aipperspach , Juergen Pille , Otto Wagner
发明人： Chad Adams , Anthony Aipperspach , Juergen Pille , Otto Wagner
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C7/06 , G11C7/1006 , G11C7/12
摘要： In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了访问存储器的第一种方法。第一种方法包括以下步骤：（1）将包含在具有排列成行和列的多个单元的存储器中的单元中存储位，其中每个单元包括一组晶体管，其适合于存储该位并影响被断言的信号在耦合到所述单元的位线上的读取操作期间，所述受影响的信号与存储在所述单元中的所述位的值相匹配; 并且（2）防止存储在单元中的位的值改变状态，同时晶体管组影响在耦合到单元的位线的读操作期间断言的信号。提供了许多其他方面。

6. 发明申请

US20070165447A1 Asymmetrical Random Access Memory Cell, A Memory Comprising Asymmetrical Memory Cells And A Method To Operate Such A Memory 有权
标题翻译：非对称随机存取存储器单元，包含不对称存储单元的存储器和一种操作这样的存储器的方法
公开(公告)号：US20070165447A1
公开(公告)日：2007-07-19
申请号：US11623443
申请日：2007-01-16
申请人： Otto Wagner , Sebastian Ehrenreich , Torsten Mahnke , Anthony Gus Aipperspach
发明人： Otto Wagner , Sebastian Ehrenreich , Torsten Mahnke , Anthony Gus Aipperspach
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (21, 31), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters (2, 3) which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors (21, 31) are driven by separate controlled wordlines (wl, wwl). Furthermore the invention relates to a random access memory comprising a plurality of such asymmetrical random access memory cells and to a method to operate such a random access memory.
摘要翻译：非对称随机存取存储单元（1）包括交叉耦合的反相器（2,3），它们通过一对互补位线的分开的位线（blt，blc）在其节点（22,32）处被驱动，所述位线连接通过通过晶体管（21,31），其中随机存取存储单元通过具有不对称物理行为的交叉耦合反相器（2,3）不对称，从而存在逆变器的不同切换阈值，并且通过 - 晶体管（21,31）由单独的受控字线（w1，wwl）驱动。此外，本发明涉及包括多个这样的非对称随机存取存储器单元的随机存取存储器和一种操作这样的随机存取存储器的方法。

7. 发明授权

US07535750B2 Asymmetrical random access memory cell, and a memory comprising asymmetrical memory cells 有权
标题翻译：不对称随机存取存储器单元，以及包含不对称存储单元的存储器
公开(公告)号：US07535750B2
公开(公告)日：2009-05-19
申请号：US11623443
申请日：2007-01-16
申请人： Otto Wagner , Sebastian Ehrenreich , Torsten Mahnke , Anthony Gus Aipperspach
发明人： Otto Wagner , Sebastian Ehrenreich , Torsten Mahnke , Anthony Gus Aipperspach
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetrical random access memory cell (1) including cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (21, 31), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters (2, 3) which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors (21, 31) are driven by separate controlled wordlines (wl, wwl).
摘要翻译：包括交叉耦合的反相器（2,3）的不对称随机存取存储器单元（1），它们通过一对互补位线的分开的位线（blt，blc）在它们的节点（22,32）处被驱动，通过通过晶体管（21,31），其中随机存取存储单元通过具有不对称物理行为的交叉耦合反相器（2,3）不对称，从而存在逆变器的不同切换阈值，并且通过 - 晶体管（21,31）由单独的受控字线（w1，wwl）驱动。

8. 发明授权

US07755394B2 Circuit combining level shift function with gated reset 失效
标题翻译：电路组合电平移位功能与门控复位
公开(公告)号：US07755394B2
公开(公告)日：2010-07-13
申请号：US12196427
申请日：2008-08-22
申请人： Thomas Froehnel , Guenter Mayer , Rolf Sautter , Otto Wagner
发明人： Thomas Froehnel , Guenter Mayer , Rolf Sautter , Otto Wagner
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/0013
摘要： A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.
摘要翻译：描述了将电平移位功能与门控复位组合的电路（01），其具有由较低电压（VD）提供的输入和在其输出端（05）以较高电压（VC）驱动的简单逻辑功能。所述电路（01）包括门控复位方案加上用于逻辑功能的装置（10,30,40）。

9. 发明申请

US20090058465A1 Circuit Combining Level Shift Function with Gated Reset 失效
标题翻译：电路组合电平移位功能与门控复位
公开(公告)号：US20090058465A1
公开(公告)日：2009-03-05
申请号：US12196427
申请日：2008-08-22
申请人： Thomas Froehnel , Guenter Mayer , Rolf Sautter , Otto Wagner
发明人： Thomas Froehnel , Guenter Mayer , Rolf Sautter , Otto Wagner
IPC分类号： H03K19/0185
CPC分类号： H03K19/018521 , H03K19/0013
摘要： A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.
摘要翻译：描述了将电平移位功能与门控复位组合的电路（01），其具有由较低电压（VD）提供的输入和在其输出端（05）以较高电压（VC）驱动的简单逻辑功能。所述电路（01）包括门控复位方案加上用于逻辑功能的装置（10,30,40）。

10. 发明申请

US20050254317A1 PROGRAMMABLE SENSE AMPLIFIER TIMING GENERATOR 失效
标题翻译：可编程感应放大器时序发生器
公开(公告)号：US20050254317A1
公开(公告)日：2005-11-17
申请号：US10844301
申请日：2004-05-12
申请人： Yuen Chan , Timothy Charest , John Rawlins , Arthur Tuminaro , Jatinder Wadhwa , Otto Wagner
发明人： Yuen Chan , Timothy Charest , John Rawlins , Arthur Tuminaro , Jatinder Wadhwa , Otto Wagner
IPC分类号： G11C7/00 , G11C7/08 , G11C7/20
CPC分类号： G11C7/20 , G11C7/08 , G11C2207/065
摘要： A SRAM sense amplifier timing circuit provides various delay settings for the sense amplifier enable signal (sae) and the sense amplifier reset signal (rse) in order to allow critical timing adjustments to be made for early mode, late mode conditions by varying the timing or with of the sense amplifier output pulse. These timing adjustments are programmable using scan in bits.
摘要翻译： SRAM读出放大器定时电路为读出放大器使能信号（sae）和读出放大器复位信号（rse）提供了各种延迟设置，以便允许通过改变时序来对早期模式，晚期模式条件进行临界定时调整，或者具有读出放大器的输出脉冲。这些定时调整可以使用扫描位进行编程。

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