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1. 发明授权

US06614265B2 Static logic compatible multiport latch 失效
公开(公告)号：US06614265B2
公开(公告)日：2003-09-02
申请号：US09683260
申请日：2001-12-05
申请人： Stefan Buettner , Guenter Mayer , Juergen Pille , Dieter Wendel
发明人： Stefan Buettner , Guenter Mayer , Juergen Pille , Dieter Wendel
IPC分类号： H03K1900
CPC分类号： H03K3/356156 , H03K3/356121 , H03K17/005 , H03K17/693
摘要： The invention describes a high-performance static logic compatible multiport latch. The latch is controlled by at least a first and a second clock (CLK 1, CLK 2), which consist of at least first and second data input ports (107, 111) with together at least three data inputs (DATA 1.1, . . . , DATA 1.n, DATA 2.1, . . . , DATA 2.n) and at least one data output (OUT). The first clock (CLK 1) controls whether data (DATA1.1, . . . , DATA 1.n) applied to the first data input ports (107) is stored in or clocked through the latch (100), the second clock (CLK 2) controls whether data (DATA 2.1, . . . , DATA 2.n) applied to the second data input ports (111) is stored in or clocked through the latch, and either the first clock (CLK 1) or the second clock (CLK 2) clocks data into the latch at the same time.

2. 发明授权

US08612500B2 Method and decimal arithmetic logic unit structure to generate a magnitude result of a mathematic 失效
标题翻译：方法和十进制算术逻辑单元结构，产生一个数学的幅度结果
公开(公告)号：US08612500B2
公开(公告)日：2013-12-17
申请号：US12013905
申请日：2008-01-14
申请人： Wilhelm Haller , Ulrich Krauch , Guenter Mayer , Eric M. Schwarz
发明人： Wilhelm Haller , Ulrich Krauch , Guenter Mayer , Eric M. Schwarz
IPC分类号： G06F15/00 , G06F7/50
CPC分类号： G06F7/4912
摘要： A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.
摘要翻译：一种在十进制算术逻辑单元结构中产生一个周期内的两个十进制操作数的数学运算的幅度结果的方法，其中十进制操作数是十六进制符号幅度格式。

3. 发明申请

US20130096901A1 Verifying Simulation Design Modifications 审中-公开
标题翻译：验证仿真设计修改
公开(公告)号：US20130096901A1
公开(公告)日：2013-04-18
申请号：US13271472
申请日：2011-10-12
申请人： Wolfgang Gellerich , Guenter Mayer , Chung-Lung K. Shum , Kai Weber
发明人： Wolfgang Gellerich , Guenter Mayer , Chung-Lung K. Shum , Kai Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A mechanism is provided for verifying design modifications to a simulation design unit included within a simulation model of an integrated electronic device. A modified description is received of a simulation design unit that failed to meet an expected physical property value during an initial simulation of the entire integrated electronic device. A simulation of the simulation design unit is executed using a list of identified input signals from a trace file. The trace file is generated during the initial simulation and indicates state values for the list of identified input signals. A determination is made as to whether the simulation of the simulation design unit fails to meet the expected physical property value. An indication is generated that modifications made to an initial description of the simulation design unit are successful in response to the simulation of the simulation design unit meeting the expected physical property value.
摘要翻译：提供了用于验证对包括在集成电子设备的仿真模型内的模拟设计单元的设计修改的机制。接收到在整个集成电子设备的初始模拟期间不能满足预期物理属性值的模拟设计单元的修改的描述。使用来自跟踪文件的已识别输入信号的列表来执行仿真设计单元的模拟。跟踪文件在初始仿真期间生成，并指示已识别输入信号列表的状态值。确定模拟设计单元的仿真是否不能满足预期的物理属性值。产生对模拟设计单元的初始描述进行的修改成功响应于满足预期物理属性值的模拟设计单元的模拟的指示。

4. 发明申请

US20090083569A1 Generating a Local Clock Domain Using Dynamic Controls 失效
标题翻译：使用动态控件生成本地时钟域
公开(公告)号：US20090083569A1
公开(公告)日：2009-03-26
申请号：US11859819
申请日：2007-09-24
申请人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
发明人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
IPC分类号： G04F10/00 , H04L7/00 , G06F1/04
CPC分类号： G06F1/04 , G06F1/3275 , G11C7/22 , G11C7/222 , G11C11/413 , Y02D10/14
摘要： A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times its commencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.
摘要翻译：一种用于在操作中产生本地时钟域的方法包括以下步骤：在操作期间接收用于逻辑的较慢部分的时钟频率测量; 产生本地信号以指示操作的开始并用作时钟选通信号; 将时钟门控信号锁存到选定的周期; 基于时钟门控信号产生时钟域控制，使得操作在所选择的周期上开始生效; 并且在未锁定的锁存器中传播时钟门控信号多个周期，使得第二操作被限制为被启动直到操作完成。

5. 发明申请

US20090058465A1 Circuit Combining Level Shift Function with Gated Reset 失效
标题翻译：电路组合电平移位功能与门控复位
公开(公告)号：US20090058465A1
公开(公告)日：2009-03-05
申请号：US12196427
申请日：2008-08-22
申请人： Thomas Froehnel , Guenter Mayer , Rolf Sautter , Otto Wagner
发明人： Thomas Froehnel , Guenter Mayer , Rolf Sautter , Otto Wagner
IPC分类号： H03K19/0185
CPC分类号： H03K19/018521 , H03K19/0013
摘要： A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.
摘要翻译：描述了将电平移位功能与门控复位组合的电路（01），其具有由较低电压（VD）提供的输入和在其输出端（05）以较高电压（VC）驱动的简单逻辑功能。所述电路（01）包括门控复位方案加上用于逻辑功能的装置（10,30,40）。

6. 发明申请

US20080071852A1 METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHMETIC UNIT PLUS ARITHMETIC UNIT TO PERFORM SUCH A METHOD 审中-公开
标题翻译：在二进制算术加法算术单元中执行两个运算符的执行的方法来执行这种方法
公开(公告)号：US20080071852A1
公开(公告)日：2008-03-20
申请号：US11855658
申请日：2007-09-14
申请人： Wilhelm Haller , Guenter Mayer , Veit Gernhoefer , Ulrich Krauch , Simon Fabel
发明人： Wilhelm Haller , Guenter Mayer , Veit Gernhoefer , Ulrich Krauch , Simon Fabel
IPC分类号： G06F7/50
CPC分类号： G06F7/507
摘要： A method and apparatus is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.
摘要翻译：提供了一种方法和装置，用于通过将两个操作数细分成相等位数的组来执行二进制运算单元中的两个操作数的减法，通过适当的算术运算，生成两个特定的位组的中间结果对分别包括相同位位置的操作数。每个中间结果对的第一个中间结果是在“0”的进位假设下产生的，并且每个中间结果对的第二个中间结果在“1”的进位假设下生成。选择来自每组比特的每个特定中间结果对的正确的中间结果，并且通过适当地合并所选择的正确的中间结果来生成两个操作数的减法的结果。

7. 发明授权

US06930902B2 Device for storing information and a method for partial write and restore 有权
标题翻译：用于存储信息的设备和用于部分写入和恢复的方法
公开(公告)号：US06930902B2
公开(公告)日：2005-08-16
申请号：US10726101
申请日：2003-12-02
申请人： Guenter Mayer , Otto Martin Wagner
发明人： Guenter Mayer , Otto Martin Wagner
IPC分类号： G11C7/12 , G11C7/18 , G11C5/06
CPC分类号： G11C7/18 , G11C7/12
摘要： A device and method for storing information including an array of memory cells organized in bitlines and wordlines. The bitlines are subdivided in sections of wordlines and the sectioned bitlines are connected to a global bitline by a connector. The connector is made bidirectional and uses the high order part of the wordline addresses for this section of bitlines as a disable reset command. The reset stays active for unselected portions, compensating leakage of a mass of unselected cells which could disturb valid read signals.
摘要翻译：一种用于存储包括以位线和字线组织的存储器单元的阵列的信息的装置和方法。位线被细分为字线部分，分段位线由连接器连接到全局位线。连接器是双向的，并将这一部分位线的字线地址的高阶部分用作禁用复位命令。复位对于未选择的部分保持有效，补偿大量未选择的单元的泄漏，这可能会干扰有效的读取信号。

8. 发明授权

US07755394B2 Circuit combining level shift function with gated reset 失效
标题翻译：电路组合电平移位功能与门控复位
公开(公告)号：US07755394B2
公开(公告)日：2010-07-13
申请号：US12196427
申请日：2008-08-22
申请人： Thomas Froehnel , Guenter Mayer , Rolf Sautter , Otto Wagner
发明人： Thomas Froehnel , Guenter Mayer , Rolf Sautter , Otto Wagner
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/0013
摘要： A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.
摘要翻译：描述了将电平移位功能与门控复位组合的电路（01），其具有由较低电压（VD）提供的输入和在其输出端（05）以较高电压（VC）驱动的简单逻辑功能。所述电路（01）包括门控复位方案加上用于逻辑功能的装置（10,30,40）。

9. 发明申请

US20090112963A1 METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHMETIC UNIT PLUS ARITHMETIC UNIT TO PERFORM SUCH A METHOD 审中-公开
标题翻译：在二进制算术加法算术单元中执行两个运算符的执行的方法来执行这种方法
公开(公告)号：US20090112963A1
公开(公告)日：2009-04-30
申请号：US11926582
申请日：2007-10-29
申请人： Wilhelm Haller , Guenter Mayer , Veit Gernhoefer , Ulrich Krauch , Simon Fabel
发明人： Wilhelm Haller , Guenter Mayer , Veit Gernhoefer , Ulrich Krauch , Simon Fabel
IPC分类号： G06F7/508
CPC分类号： G06F7/507
摘要： A method, circuit apparatus, and a design structure on which the circuit resides, is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.
摘要翻译：提供电路所在的方法，电路装置和设计结构，以通过将两个操作数细分为相等位数的组来执行二进制运算单元中的两个操作数的减法，通过适当的算术运算生成对分别包含相同比特位置的两个操作数的特定的比特组的中间结果。每个中间结果对的第一个中间结果是在“0”的进位假设下产生的，并且每个中间结果对的第二个中间结果在“1”的进位假设下生成。选择来自每组比特的每个特定中间结果对的正确的中间结果，并且通过适当地合并所选择的正确的中间结果来生成两个操作数的减法的结果。

10. 发明授权

US06341093B1 SOI array sense and write margin qualification 失效
标题翻译： SOI阵列感和写裕度资格
公开(公告)号：US06341093B1
公开(公告)日：2002-01-22
申请号：US09872885
申请日：2001-06-01
申请人： Martin Eckert , Guenter Mayer , Juergen Pille , Dieter Wendel
发明人： Martin Eckert , Guenter Mayer , Juergen Pille , Dieter Wendel
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C11/41
摘要： The present invention relates to storage devices and in particular, it relates to a method for testing the storage quality of history dependent memory array cells. A cell can be stressed selectively with predetermined test conditions such that these test conditions cover all of the hardware status distribution which might arise when the cell is operated under the full range of operating conditions. This is basically achieved by cutting off a predetermined cutoff width of the trailing edge of the active wordline select pulse.
摘要翻译：本发明涉及存储装置，特别涉及用于测试历史依赖存储器阵列单元的存储质量的方法。可以用预定的测试条件选择性地对电池进行应力，使得这些测试条件覆盖当电池在全部工作条件下操作时可能出现的所有硬件状态分布。这主要通过切断有效字线选择脉冲的后沿的预定截止宽度来实现。

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