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1. 发明授权

US07289370B2 Methods and apparatus for accessing memory 有权
公开(公告)号：US07289370B2
公开(公告)日：2007-10-30
申请号：US11186606
申请日：2005-07-21
申请人： Chad Allen Adams , Anthony Gus Aipperspach , Juergen Pille , Otto Wagner
发明人： Chad Allen Adams , Anthony Gus Aipperspach , Juergen Pille , Otto Wagner
IPC分类号： G11C16/04
CPC分类号： G11C11/413 , G11C7/06 , G11C7/1006 , G11C7/12
摘要： In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.

2. 发明申请

US20080080259A1 6 Transistor Memory Circuit Pair Supporting Simultaneous Read/Write and Method Therefore 审中-公开
标题翻译： 6晶体管存储电路对支持同时读/写和方法因此
公开(公告)号：US20080080259A1
公开(公告)日：2008-04-03
申请号：US11862235
申请日：2007-09-27
申请人： Stefan Buettner , Juergen Pille , Otto Wagner , Dieter Wendel
发明人： Stefan Buettner , Juergen Pille , Otto Wagner , Dieter Wendel
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/18
摘要： A method and memory circuit comprising a plurality of cells accessible by word lines and bit lines is described, wherein each cell includes a group of six transistors adapted to both store a bit inserted into the cell during a write operation and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell, wherein the word lines and bit lines of the memory are divided into sections assigned to groups of equal numbers of cells, wherein said sections are individually accessible for read or write operations such that one cell of a group can be read simultaneously while writing another cell of the group.
摘要翻译：描述了包括由字线和位线可访问的多个单元的方法和存储器电路，其中每个单元包括一组六个晶体管，其适于在写操作期间存储插入到单元中的位，并且影响在在耦合到该单元的位线上读取操作，使得受影响的信号与存储在单元中的位的值相匹配，其中存储器的字线和位线被分成分配给相同数量的单元的组，其中所述部分可单独访问用于读取或写入操作，使得可以同时读取组中的一个单元同时写入该组的另一个单元。

3. 发明申请

US20070019461A1 Methods and apparatus for accessing memory 有权
标题翻译：访问内存的方法和设备
公开(公告)号：US20070019461A1
公开(公告)日：2007-01-25
申请号：US11186606
申请日：2005-07-21
申请人： Chad Adams , Anthony Aipperspach , Juergen Pille , Otto Wagner
发明人： Chad Adams , Anthony Aipperspach , Juergen Pille , Otto Wagner
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C7/06 , G11C7/1006 , G11C7/12
摘要： In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了访问存储器的第一种方法。第一种方法包括以下步骤：（1）将包含在具有排列成行和列的多个单元的存储器中的单元中存储位，其中每个单元包括一组晶体管，其适合于存储该位并影响被断言的信号在耦合到所述单元的位线上的读取操作期间，所述受影响的信号与存储在所述单元中的所述位的值相匹配; 并且（2）防止存储在单元中的位的值改变状态，同时晶体管组影响在耦合到单元的位线的读操作期间断言的信号。提供了许多其他方面。

4. 发明授权

US07813163B2 Single-ended read and differential write scheme 失效
标题翻译：单端读和差分写入方案
公开(公告)号：US07813163B2
公开(公告)日：2010-10-12
申请号：US12190680
申请日：2008-08-13
申请人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
发明人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.
摘要翻译：提供了读取和写入至少一个静态存储单元的方法，所述单元包括交叉耦合的反相器对和两个通过器件，其中所述方法的特征在于，在只读选择两个通过器件中的一个的同时，对于写入，选择了传递设备。此外，描述了读取和写入至少一个静态存储器单元的电路，所述单元包括交叉耦合的反相器对和两个通过器件。所述电路的特征在于，对于单元的每个通过器件，单个字线与特定通过器件的栅极连接，其中两个字线被选择用于写入，并且单个字线被选择用于读取。

5. 发明申请

US20090059688A1 Single-ended read and differential write scheme 失效
标题翻译：单端读和差分写入方案
公开(公告)号：US20090059688A1
公开(公告)日：2009-03-05
申请号：US12190680
申请日：2008-08-13
申请人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
发明人： Juergen Pille , Otto Wagner , Sebastian Ehrenreich , Rolf Sautter
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C11/413
摘要： A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.
摘要翻译：提供了读取和写入至少一个静态存储单元的方法，所述单元包括交叉耦合的反相器对和两个通过器件，其中所述方法的特征在于，在只读选择两个通过器件中的一个的同时，对于写入，选择了传递设备。此外，描述了读取和写入至少一个静态存储器单元的电路，所述单元包括交叉耦合的反相器对和两个通过器件。所述电路的特征在于，对于单元的每个通过器件，单个字线与特定通过器件的栅极连接，其中两个字线被选择用于写入，并且单个字线被选择用于读取。

6. 发明授权

US08493812B2 Boost circuit for generating an adjustable boost voltage 失效
标题翻译：用于产生可调节升压电压的升压电路
公开(公告)号：US08493812B2
公开(公告)日：2013-07-23
申请号：US12913929
申请日：2010-10-28
申请人： Osama Dengler , Alexander Fritsch , Wolfgang Penth , Juergen Pille
发明人： Osama Dengler , Alexander Fritsch , Wolfgang Penth , Juergen Pille
IPC分类号： G11C8/08
CPC分类号： G11C5/145
摘要： A technique for generating an adjustable boost voltage for a device includes charging, using first and second switches, a capacitor to a first voltage during a charging phase. The technique also includes stacking, using a third switch, a second voltage onto the first voltage across the capacitor in a boost phase to generate a boost voltage. In this case, the boost voltage is applied to a driver circuit of the device only during the boost phase and at least one of the first and second voltages is adjustable, thereby making the boost voltage adjustable.
摘要翻译：用于产生用于装置的可调升压电压的技术包括在充电阶段期间使用第一和第二开关将电容器充电到第一电压。该技术还包括使用第三开关将第二电压堆叠在升压阶段的电容器两端的第一电压上以产生升压电压。在这种情况下，升压电压仅在升压阶段被施加到器件的驱动电路，并且第一和第二电压中的至少一个是可调节的，从而使升压电压可调。

7. 发明授权

US07844799B2 Method and system for pipeline reduction 有权
标题翻译：减少管道的方法和系统
公开(公告)号：US07844799B2
公开(公告)日：2010-11-30
申请号：US09683383
申请日：2001-12-20
申请人： Jens Leenstra , Antje Mueller , Juergen Pille , Dieter Wendel
发明人： Jens Leenstra , Antje Mueller , Juergen Pille , Dieter Wendel
IPC分类号： G06F9/30 , G06F9/34
CPC分类号： G06F9/3873 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： A method and system for operating a high frequency out-of-order processor with increased pipeline length. A new scheme is disclosed to reduce the pipeline by the detection and exploitation of so called “no dependency” for an instruction. A “no dependency” signal tells that all required source data is available for the instruction at least one cycle before the source data valid bit(s) are inserted into the issue queue. Therefore, one or more stages of the pipeline are bypassed.
摘要翻译：一种用于操作具有增加的管道长度的高频无序处理器的方法和系统。公开了一种新方案，通过对指令的所谓“不依赖”的检测和利用来减少流水线。 “无依赖”信号指示在将源数据有效位插入到发出队列之前至少一个周期，所有必需的源数据可用于指令。因此，管道的一个或多个阶段被绕过。

8. 发明申请

US20060179396A1 Redundancy in signal distribution trees 有权
标题翻译：信号分配树的冗余
公开(公告)号：US20060179396A1
公开(公告)日：2006-08-10
申请号：US11350149
申请日：2006-02-08
申请人： Sebastian Ehrenreich , Juergen Koehl , Juergen Pille
发明人： Sebastian Ehrenreich , Juergen Koehl , Juergen Pille
IPC分类号： H03M13/00
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/007
摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/or preceding sub tree.
摘要翻译：一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到邻近的相邻树（12）路径的次级输入（32）的信号组合，以及 /或前一个子树。

9. 发明授权

US06537861B1 SOI transistor with body contact and method of forming same 失效
标题翻译：具有体接触的SOI晶体管及其形成方法
公开(公告)号：US06537861B1
公开(公告)日：2003-03-25
申请号：US09382108
申请日：1999-08-24
申请人： Karl-Eugen Kroell , Juergen Pille , Helmut Schettler
发明人： Karl-Eugen Kroell , Juergen Pille , Helmut Schettler
IPC分类号： H01L2100
CPC分类号： H01L29/66772 , H01L29/7841 , H01L29/78615
摘要： An SOI field effect transistor is provided comprising a body contact that is isolated by a shallow trench that is formed into the body portion of the transistor, thereby eliminating any increase in gate capacitance or delay. A method of forming such a transistor is provided that does not require any additional process steps.
摘要翻译：提供SOI场效应晶体管，其包括由形成在晶体管的主体部分中的浅沟槽隔离的体接触，从而消除栅极电容或延迟的任何增加。提供了一种形成这种晶体管的方法，其不需要任何额外的工艺步骤。

10. 发明授权

US06341093B1 SOI array sense and write margin qualification 失效
标题翻译： SOI阵列感和写裕度资格
公开(公告)号：US06341093B1
公开(公告)日：2002-01-22
申请号：US09872885
申请日：2001-06-01
申请人： Martin Eckert , Guenter Mayer , Juergen Pille , Dieter Wendel
发明人： Martin Eckert , Guenter Mayer , Juergen Pille , Dieter Wendel
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C11/41
摘要： The present invention relates to storage devices and in particular, it relates to a method for testing the storage quality of history dependent memory array cells. A cell can be stressed selectively with predetermined test conditions such that these test conditions cover all of the hardware status distribution which might arise when the cell is operated under the full range of operating conditions. This is basically achieved by cutting off a predetermined cutoff width of the trailing edge of the active wordline select pulse.
摘要翻译：本发明涉及存储装置，特别涉及用于测试历史依赖存储器阵列单元的存储质量的方法。可以用预定的测试条件选择性地对电池进行应力，使得这些测试条件覆盖当电池在全部工作条件下操作时可能出现的所有硬件状态分布。这主要通过切断有效字线选择脉冲的后沿的预定截止宽度来实现。

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