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1. 发明授权

US07817481B2 Column selectable self-biasing virtual voltages for SRAM write assist 有权
标题翻译：列可选择自偏压虚拟电压用于SRAM写入辅助
公开(公告)号：US07817481B2
公开(公告)日：2010-10-19
申请号：US12167300
申请日：2008-07-03
申请人： Chad Allen Adams , George M. Braceras , Todd A. Christensen , Harold Pilo
发明人： Chad Allen Adams , George M. Braceras , Todd A. Christensen , Harold Pilo
IPC分类号： G11C7/22 , G11C11/00 , G11C5/14
CPC分类号： G11C11/417 , G11C11/41 , G11C11/419
摘要： A static random access memory decoder circuit includes a first cell supply line coupled to provide a first column of memory cells a first cell supply voltage and a second cell supply line coupled to provide a first column of memory cells a first cell supply voltage. The decoder circuit further includes a write assist circuit having a first threshold transistor coupled to the first cell supply line and a second threshold transistor coupled to the second cell supply line. In response to a write assist signal, the write assist circuit connects one of the first and second cell supply lines selected by control circuitry to an associated one of the first and second threshold transistors, such that a cell supply voltage of the selected one of the first and second cell supply lines is reduced toward the threshold voltage of the threshold transistor.
摘要翻译：静态随机存取存储器解码器电路包括第一单元电源线，其被耦合以提供第一列存储器单元第一单元电源电压和耦合以提供第一列存储器单元的第一单元电源电压的第二单元电源线。解码器电路还包括具有耦合到第一单元电源线的第一阈值晶体管和耦合到第二单元电源线的第二阈值晶体管的写辅助电路。响应于写入辅助信号，写入辅助电路将由控制电路选择的第一和第二单元电源线之一连接到第一和第二阈值晶体管中的相关联的一个，使得所选择的一个的单元电源电压第一和第二电池供应线路朝阈值晶体管的阈值电压减小。

2. 发明申请

US20090116298A1 APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION 失效
标题翻译：用于实现SRAM单元写入性能评估的设备
公开(公告)号：US20090116298A1
公开(公告)日：2009-05-07
申请号：US12351920
申请日：2009-01-12
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译： SRAM单元写入性能评估电路包括SRAM核心，其中每个字线仅连接到一个位列。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

3. 发明授权

US07480170B1 Method and apparatus for implementing enhanced SRAM read performance sort ring oscillator (PSRO) 有权
标题翻译：实现增强型SRAM读取性能排序环形振荡器（PSRO）的方法和装置
公开(公告)号：US07480170B1
公开(公告)日：2009-01-20
申请号：US11782808
申请日：2007-07-25
申请人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
发明人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
IPC分类号： G11C11/40
CPC分类号： G11C11/413 , G11C11/41 , G11C11/419 , G11C2029/0403
摘要： A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.
摘要翻译：包括静态随机存取存储器（SRAM）单元的方法和装置实现增强型SRAM读取性能排序环形振荡器（PSRO）。一对并联反极性连接的反相器定义了静态锁存器或交叉耦合存储器单元。 SRAM单元包括独立的左和右字线，为用于访问存储单元的一对存取晶体管提供相应的栅极输入。 SRAM单元包括到静态锁存器的一侧的电压供应连接。例如，静态锁存器的补码侧连接到电源。多个SRAM单元组装在一起以形成SRAM基块。多个SRAM基块被连接在一起以形成SRAM读取PSRO。

4. 发明授权

US07289370B2 Methods and apparatus for accessing memory 有权
公开(公告)号：US07289370B2
公开(公告)日：2007-10-30
申请号：US11186606
申请日：2005-07-21
申请人： Chad Allen Adams , Anthony Gus Aipperspach , Juergen Pille , Otto Wagner
发明人： Chad Allen Adams , Anthony Gus Aipperspach , Juergen Pille , Otto Wagner
IPC分类号： G11C16/04
CPC分类号： G11C11/413 , G11C7/06 , G11C7/1006 , G11C7/12
摘要： In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.

5. 发明申请

US20060087873A1 METHOD AND SUM ADDRESSED CELL ENCODER FOR ENHANCED COMPARE AND SEARCH TIMING FOR CAM COMPARE 有权
标题翻译：用于CAM比较的增强比较和搜索时序的方法和寻址小区编码器
公开(公告)号：US20060087873A1
公开(公告)日：2006-04-27
申请号：US10970522
申请日：2004-10-21
申请人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
发明人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A method and a sum addressed content-addressable memory (CAM) compare are provided for implementing an enhanced sum address compare function. True and compliment bit signals applied to the CAM compare are encoded by combining respective ones of the applied true and compliment bit signals. Then the encoded true and compliment bit signals are applied to a critical path dynamic compare circuit. An encoder apparatus encodes true and compliment bit signals that then are applied to the dynamic compare circuit in the critical path.
摘要翻译：提供了一种方法和和寻址内容寻址存储器（CAM）比较，用于实现增强的和地址比较功能。应用于CAM比较的真实和补码比特信号通过组合所应用的真实和补码比特信号中的相应的一些来进行编码。然后将编码的真实和补码位信号应用于关键路径动态比较电路。编码器装置对真实和补码比特信号进行编码，然后将其应用于关键路径中的动态比较电路。

6. 发明授权

US07035127B1 Method and sum addressed cell encoder for enhanced compare and search timing for CAM compare 有权
标题翻译：方法和和寻址单元编码器，用于CAM比较的增强比较和搜索时序
公开(公告)号：US07035127B1
公开(公告)日：2006-04-25
申请号：US10970522
申请日：2004-10-21
申请人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
发明人： Chad Allen Adams , Derick Gardner Behrends , Todd Alan Christensen , Peter Thomas Freiburger , Ryan Charles Kivimagi
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A method and a sum addressed content-addressable memory (CAM) compare are provided for implementing an enhanced sum address compare function. True and compliment bit signals applied to the CAM compare are encoded by combining respective ones of the applied true and compliment bit signals. Then the encoded true and compliment bit signals are applied to a critical path dynamic compare circuit. An encoder apparatus encodes true and compliment bit signals that then are applied to the dynamic compare circuit in the critical path.
摘要翻译：提供了一种方法和和寻址内容寻址存储器（CAM）比较，用于实现增强的和地址比较功能。应用于CAM比较的真实和补码比特信号通过组合所应用的真实和补码比特信号中的相应的一些来进行编码。然后将编码的真实和补码位信号应用于关键路径动态比较电路。编码器装置对真实和补码比特信号进行编码，然后将其应用于关键路径中的动态比较电路。

7. 发明授权

US07788554B2 Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluation 失效
标题翻译：体现在用于实现SRAM单元写入性能评估的机器可读介质中的设计结构
公开(公告)号：US07788554B2
公开(公告)日：2010-08-31
申请号：US11873173
申请日：2007-10-16
申请人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
发明人： Chad Allen Adams , Derick Gardner Behrends , Travis Reynold Hebig , Daniel Mark Nelson
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/1202
摘要： A design structure embodied in a machine readable medium for implementing static random access memory (SRAM) cell write performance evaluation is provided. A SRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified.
摘要翻译：提供了体现在用于实现静态随机存取存储器（SRAM）单元写入性能评估的机器可读介质中的设计结构。 SRAM内核包括只连接到一个位列的每个字线。环形振荡器电路用于产生字线脉冲。状态机控制包括环形振荡器电路和SRAM内核的SRAM单元写入性能评估电路的操作。将控制信号施加到状态机以选择第一写入操作，其中电路同时将所有单元格写入具有宽字线的已知状态，以确保所有单元都被写入。然后选择第二次写入操作，同时启动所有字线，将单元写入相反的状态。从这些写入操作中，识别要写入单元的所需字线脉冲宽度。

8. 发明授权

US07684263B2 Method and circuit for implementing enhanced SRAM write and read performance ring oscillator 失效
标题翻译：实现增强型SRAM写和读性能环形振荡器的方法和电路
公开(公告)号：US07684263B2
公开(公告)日：2010-03-23
申请号：US12015806
申请日：2008-01-17
申请人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
发明人： Chad Allen Adams , Todd Alan Christensen , Peter Thomas Freiburger , Travis Reynold Hebig
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A method and circuit for implementing an enhanced static random access memory (SRAM) read and write performance ring oscillator, and a design structure on which the subject circuit resides are provided. A plurality of SRAM base blocks is connected together in a chain. Each of the plurality of SRAM base blocks includes a SRAM cell, such as an eight-transistor (8T) static random access memory (SRAM) cell, and a local evaluation block coupled to the SRAM cell. The SRAM cell includes independent left wordline input and right wordline input. The SRAM cell includes a read wordline connected high, and a true and complement write bitline pair connected low. In the local evaluation circuit, one input of a NAND gate receiving the read bitline input is connected high. A control signal is combined with an inverted feedback signal to start and stop the ring oscillator.
摘要翻译：一种用于实现增强型静态随机存取存储器（SRAM）读写性能环形振荡器的方法和电路，以及设置有被摄体电路所在的设计结构。多个SRAM基块在链中连接在一起。多个SRAM基块中的每一个包括诸如八晶体管（8T）静态随机存取存储器（SRAM）单元的SRAM单元，以及耦合到SRAM单元的局部评估块。 SRAM单元包括独立的左字线输入和右字线输入。 SRAM单元包括一个连接到高电平的读字字线和一个连接低电平的真写补码写位线对。在本地评估电路中，接收读取位线输入的NAND门的一个输入被连接得很高。控制信号与反相反馈信号相结合，以启动和停止环形振荡器。

9. 发明申请

US20090285039A1 METHOD AND APPARATUS FOR LOCALLY GENERATING A VIRTUAL GROUND FOR WRITE ASSIST ON COLUMN SELECTED SRAM CELLS 审中-公开
标题翻译：用于在列选择的SRAM电池上为写入辅助装置的虚拟地线生成的方法和装置
公开(公告)号：US20090285039A1
公开(公告)日：2009-11-19
申请号：US12121553
申请日：2008-05-15
申请人： Chad Allen Adams , Elizabeth Lair Gerhard , Sharon Huertas Cesky , Jeffrey Milton Scherer
发明人： Chad Allen Adams , Elizabeth Lair Gerhard , Sharon Huertas Cesky , Jeffrey Milton Scherer
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A method and apparatus for write assist for a static random access memory (SRAM) array, is provided, which increases the write ability of the SRAM cell by locally raising the source voltage. One embodiment involves locally generating a virtual ground for write assist on column selected SRAM cells, including locally raising the source voltage to increase the write ability of the SRAM cell; wherein locally raising the source voltage comprises locally generating a virtual source/ground node for boosting the write ability of a column of SRAM cells without using an additional on-chip or off-chip supply; thereby decreasing the voltage differential across the source and supply of the column of SRAM cells during a write, and restoring the standard chip differential during a read.
摘要翻译：提供了一种用于静态随机存取存储器（SRAM）阵列的写辅助的方法和装置，其通过局部提高源电压来增加SRAM单元的写入能力。一个实施例涉及在列选择的SRAM单元上本地产生用于写入辅助的虚拟地，包括本地提高源电压以增加SRAM单元的写入能力; 其中局部提高源电压包括本地产生虚拟源/接地节点，用于在不使用额外的片上或片外电源的情况下提高SRAM单元的列的写入能力; 从而在写入期间降低源极之间的电压差并提供SRAM单元的列，以及在读取期间恢复标准芯片差分。

10. 发明申请

US20090027945A1 Method and Apparatus for Implementing Enhanced SRAM Read Performance Sort Ring Oscillator (PSRO) 有权
标题翻译：实现增强型SRAM读取性能排序环形振荡器（PSRO）的方法和装置
公开(公告)号：US20090027945A1
公开(公告)日：2009-01-29
申请号：US11873534
申请日：2007-10-17
申请人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
发明人： Chad Allen Adams , Todd Alan Christensen , Travis Reynold Hebig , Kirk David Peterson
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.
摘要翻译：一种包括静态随机存取存储器（SRAM）单元的方法和装置实现增强的SRAM读取性能排序环形振荡器（PSRO），以及设置有被摄体电路所在的设计结构。一对并联反极性连接的反相器定义了静态锁存器或交叉耦合存储器单元。 SRAM单元包括独立的左和右字线，为用于访问存储单元的一对存取晶体管提供相应的栅极输入。 SRAM单元包括到静态锁存器的一侧的电压供应连接。例如，静态锁存器的补码侧连接到电源。多个SRAM单元组装在一起以形成SRAM基块。多个SRAM基块被连接在一起以形成SRAM读取PSRO。

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