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    • 4. 发明授权
    • Using ONO as hard mask to reduce STI oxide loss on low voltage device in
flash or EPROM process
    • 使用ONO作为硬掩模,以减少闪存或EPROM工艺中低电压器件的STI氧化物损耗
    • US06130168A
    • 2000-10-10
    • US349844
    • 1999-07-08
    • Wen-Ting ChuDi-Son KuoChrong-Jung LinHung-Der SuJong Chen
    • Wen-Ting ChuDi-Son KuoChrong-Jung LinHung-Der SuJong Chen
    • H01L21/32H01L21/8234H01L21/8247H01L27/105H01L21/302
    • H01L27/11526H01L21/32H01L21/823462H01L21/823481H01L27/105H01L27/11546Y10S438/954
    • A new method of forming differential gate oxide thicknesses for both high and low voltage transistors is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas by shallow trench isolation regions. A polysilicon layer is deposited overlying a tunneling oxide layer on the surface of the substrate. The polysilicon and tunneling oxide layers are removed except in the memory cell area. An ONO layer is deposited overlying the polysilicon layer in the memory cell area and on the surface of the substrate in the low voltage and high voltage areas. The ONO layer is removed in the high voltage area. The substrate is oxidized in the high voltage area to form a thick gate oxide layer. Thereafter, the ONO layer is removed in the low voltage area and the substrate is oxidized to form a thin gate oxide layer. A second polysilicon layer is deposited over the ONO layer in the memory area, over the thin gate oxide layer in the low voltage area, and over the thick gate oxide layer in the high voltage area. The second polysilicon layer, ONO layer and first polysilicon layer in the memory cell area are patterned to form a control gate overlying a floating gate separated by the ONO layer. The second polysilicon layer is patterned to form a low voltage transistor in the low voltage area and a high voltage transistor in the high voltage area.
    • 描述了为高压和低压晶体管形成差分栅极氧化物厚度的新方法。 提供半导体衬底,其中衬底的有源区域通过浅沟槽隔离区域与其它有源区域隔离。 沉积在衬底表面上的隧道氧化物层上的多晶硅层。 去除多晶硅和隧道氧化物层,除了在存储单元区域中。 沉积在存储单元区域中的多晶硅层和低电压和高电压区域的衬底表面上的ONO层。 在高电压区域中去除ONO层。 衬底在高压区域被氧化以形成厚的栅极氧化物层。 此后,在低电压区域中去除ONO层,并且衬底被氧化以形成薄的栅极氧化物层。 第二多晶硅层沉积在存储区域中的ONO层上,在低电压区域的薄栅极氧化物层上方,以及高电压区域中的厚栅极氧化物层上方。 将存储单元区域中的第二多晶硅层,ONO层和第一多晶硅层图案化以形成覆盖由ONO层分离的浮动栅极的控制栅极。 将第二多晶硅层图案化以在低电压区域中形成低压晶体管,并在高电压区域形成高压晶体管。
    • 6. 发明授权
    • Method of making embedded flash memory with salicide and sac structure
    • 制造具有自杀和囊结构的嵌入式闪存的方法
    • US6074915A
    • 2000-06-13
    • US135044
    • 1998-08-17
    • Jong ChenChrong Jung LinHung-Der SuDi-Son Kuo
    • Jong ChenChrong Jung LinHung-Der SuDi-Son Kuo
    • H01L21/8247
    • H01L27/11526H01L27/11536
    • A combined method of fabricating embedded flash memory cells having salicide and self-aligned contact (SAC) structures is disclosed. The SAC structure of the cell region and the salicide contacts of the peripheral region of the semiconductor device are formed using a single mask. This is accomplished by a judicious sequence of formation and removal of the various layers including the doped first and second polysilicon layers in the memory cell and of the intrinsic polysilicon layer used in the peripheral circuits. Thus, the etching of the self-aligned contact hole of the memory cell is accomplished at the same time the salicided contact hole of the peripheral region is formed. Furthermore, the thin and thick portions of the dual-gate oxide of the two regions are formed as a natural part of the total process without having to resort to photoresist masking of one portion of the gate oxide layer with the attendant contamination problems while removing the portion of the gate oxide in the other region of the substrate.
    • 公开了一种制造具有自对准接触(SAC)结构的嵌入式闪存单元的组合方法。 半导体器件的周边区域的单元区域和硅化物触点的SAC结构使用单个掩模形成。 这是通过明确的形成和去除包括存储单元中的掺杂的第一和第二多晶硅层以及在外围电路中使用的本征多晶硅层的各种层的顺序来实现的。 因此,存储单元的自对准接触孔的蚀刻同时实现了周边区域的浸渍接触孔。 此外,两个区域的双栅极氧化物的薄而厚的部分形成为总工艺的天然部分,而不必诉诸于栅极氧化物层的一部分的光致抗蚀剂掩模以及伴随的污染问题,同时去除 栅极氧化物在衬底的另一区域中的部分。
    • 8. 发明授权
    • Method to fabricate a flash memory cell with a planar stacked gate
    • 用平面堆叠栅极制造闪存单元的方法
    • US06495880B2
    • 2002-12-17
    • US09760309
    • 2001-01-16
    • Chrong Jung LinJong ChenHung-Der SuDi-Son Kuo
    • Chrong Jung LinJong ChenHung-Der SuDi-Son Kuo
    • H01L29788
    • H01L27/11521H01L29/66825
    • A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.
    • 描述了一种制造具有改进的堆叠栅极拓扑的堆叠栅极闪存EEPROM器件的新方法。 在半导体衬底上形成隔离区。 隧道氧化物层设置在半导体衬底的表面上。 沉积在隧道氧化物层上的第一多晶硅层。 将第一多晶硅层抛光直到多晶硅的顶表面平坦并平行于半导体衬底的顶表面。 蚀刻掉第一多晶硅层以形成浮栅。 源极和漏极区域形成在半导体衬底内。 沉积在第一多晶硅层上的多层介电层。 第二多晶硅层沉积在叠层电介质层上。 蚀刻掉第二多晶硅层和互聚电介质层以形成覆盖浮栅的控制栅极。 绝缘层沉积在氧化层和控制栅上。 通过绝缘层到底层的控制栅极和底层的源极和漏极区域形成接触开口。 接触开口填充有导电层以完成闪速EEPROM装置的制造。