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1. 发明授权

US6127227A Thin ONO thickness control and gradual gate oxidation suppression by b. N.su2 treatment in flash memory 有权
标题翻译：闪存中通过N2处理对ONO厚度进行薄膜控制和逐步门极氧化抑制
公开(公告)号：US6127227A
公开(公告)日：2000-10-03
申请号：US236491
申请日：1999-01-25
申请人： Chrong Jung Lin , Jong Chen , Hung-Der Su , Di-Son Kuo
发明人： Chrong Jung Lin , Jong Chen , Hung-Der Su , Di-Son Kuo
IPC分类号： H01L21/28 , H01L29/51 , H01L21/8247
CPC分类号： H01L21/28211 , H01L21/28273 , H01L29/511
摘要： A method of forming a flash memory cell is disclosed where nitrogen treatment or implantation is employed. Nitrogen introduced into the upper layers of the polysilicon of the floating gate is instrumental in forming an unusually thin layer comprising nitrogen-oxygen-silicon. This N--O--Si layer is formed while growing the bottom oxide layer of the oxide-nitride-oxide, or ONO, the intergate layer between the floating gate and the control gate of the flash memory cell. Nitrogen in the first polysilicon layer provides control for the thickness of the bottom oxide while at the same time suppressing the gradual gate oxidation (GGO) effect in the floating gate. The now augmented ONO composite through the N--O--Si layer provides an enhanced intergate dielectric and hence, a flash memory cell with more precise coupling ratio and better performance.
摘要翻译：公开了一种形成闪存单元的方法，其中采用氮气处理或植入。引入浮栅的多晶硅的上层的氮有助于形成包含氮 - 氧 - 硅的异常薄的层。在生长氧化物 - 氮化物 - 氧化物的底部氧化物层（ONO）的同时，在浮动栅极和闪存单元的控制栅极之间形成栅极层，形成N-O-Si层。第一多晶硅层中的氮提供对底部氧化物的厚度的控制，同时抑制浮动栅极中的逐渐栅极氧化（GGO）效应。现在通过N-O-Si层增强的ONO复合材料提供增强的隔间电介质，因此提供具有更精确的耦合比和更好性能的闪存单元。

2. 发明授权

US6133096A Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices 失效
标题翻译：用于同时制造堆叠栅极闪存单元和浸液式周边器件的工艺
公开(公告)号：US6133096A
公开(公告)日：2000-10-17
申请号：US208917
申请日：1998-12-10
申请人： Hung-Der Su , Jong Chen , Chrong-Jung Lin , Di-Son Kuo
发明人： Hung-Der Su , Jong Chen , Chrong-Jung Lin , Di-Son Kuo
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11534
摘要： A process for integrating the fabrication of a flash memory cell, on a first region of a semiconductor substrate, with the fabrication of salicided peripheral devices, on a second region of the semiconductor substrate, has been developed. The flash memory cell features SAC contact structures, located between stacked gate structures, contacting underlying source/drain regions. The stack gate structures are comprised of a polycide control gate shape, on a dielectric layer, overlying a polysilicon floating gate shape. The performance of the peripheral devices are increased via use of metal silicide layers, located on the top surface of a polysilicon gate structure, as well as on the adjacent heavily doped source/drain regions.
摘要翻译：已经开发了在半导体衬底的第二区域上将闪存单元的制造在半导体衬底的第一区域上与制造水银外围器件进行集成的工艺。闪存单元具有位于层叠栅极结构之间的SAC接触结构，接触下层的源/漏区。堆叠栅极结构由覆盖多晶硅浮栅形状的介电层上的多晶硅控制栅极形状构成。通过使用位于多晶硅栅极结构的顶表面上的金属硅化物层以及相邻的重掺杂源极/漏极区域来增加外围器件的性能。

3. 发明授权

US6074915A Method of making embedded flash memory with salicide and sac structure 有权
标题翻译：制造具有自杀和囊结构的嵌入式闪存的方法
公开(公告)号：US6074915A
公开(公告)日：2000-06-13
申请号：US135044
申请日：1998-08-17
申请人： Jong Chen , Chrong Jung Lin , Hung-Der Su , Di-Son Kuo
发明人： Jong Chen , Chrong Jung Lin , Hung-Der Su , Di-Son Kuo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L27/11536
摘要： A combined method of fabricating embedded flash memory cells having salicide and self-aligned contact (SAC) structures is disclosed. The SAC structure of the cell region and the salicide contacts of the peripheral region of the semiconductor device are formed using a single mask. This is accomplished by a judicious sequence of formation and removal of the various layers including the doped first and second polysilicon layers in the memory cell and of the intrinsic polysilicon layer used in the peripheral circuits. Thus, the etching of the self-aligned contact hole of the memory cell is accomplished at the same time the salicided contact hole of the peripheral region is formed. Furthermore, the thin and thick portions of the dual-gate oxide of the two regions are formed as a natural part of the total process without having to resort to photoresist masking of one portion of the gate oxide layer with the attendant contamination problems while removing the portion of the gate oxide in the other region of the substrate.
摘要翻译：公开了一种制造具有自对准接触（SAC）结构的嵌入式闪存单元的组合方法。半导体器件的周边区域的单元区域和硅化物触点的SAC结构使用单个掩模形成。这是通过明确的形成和去除包括存储单元中的掺杂的第一和第二多晶硅层以及在外围电路中使用的本征多晶硅层的各种层的顺序来实现的。因此，存储单元的自对准接触孔的蚀刻同时实现了周边区域的浸渍接触孔。此外，两个区域的双栅极氧化物的薄而厚的部分形成为总工艺的天然部分，而不必诉诸于栅极氧化物层的一部分的光致抗蚀剂掩模以及伴随的污染问题，同时去除栅极氧化物在衬底的另一区域中的部分。

4. 发明授权

US06724036B1 Stacked-gate flash memory cell with folding gate and increased coupling ratio 有权
标题翻译：具有折叠浮动栅极的叠栅式闪存单元和增加的耦合比
公开(公告)号：US06724036B1
公开(公告)日：2004-04-20
申请号：US09654776
申请日：2000-09-05
申请人： Chia-Ta Hsieh , Di-Son Kuo , Yai-Fen Lin , Chrong Jung Lin , Jong Chen , Hung-Der Su
发明人： Chia-Ta Hsieh , Di-Son Kuo , Yai-Fen Lin , Chrong Jung Lin , Jong Chen , Hung-Der Su
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： A stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling is described. An unconventionally high isolation oxide layer is formed in a shallow trench isolation (STI) in a substrate. The deep opening in the space between the STIs is conformally lined with a polysilicon to form a floating gate extending above the opening. A conformal intergate oxide lines the entire floating gate. A layer of polysilicon overlays the intergate oxide and protrudes downward into the openings to form a control gate with increased coupling to the floating gate.
摘要翻译：描述了具有高阶氧化物和高横向耦合的浅沟槽隔离的堆叠栅极闪存单元。在衬底中的浅沟槽隔离（STI）中形成非常规的高隔离氧化层。在STI之间的空间中的深开口共形地衬有多晶硅以形成在开口上方延伸的浮动栅极。保形隔离层氧化物对整个浮动栅线进行排列。一层多晶硅覆盖了间隔栅极氧化物并向下突出到开口中，以形成一个与浮动栅极增加耦合的控制栅极。

5. 发明授权

US06495880B2 Method to fabricate a flash memory cell with a planar stacked gate 有权
标题翻译：用平面堆叠栅极制造闪存单元的方法
公开(公告)号：US06495880B2
公开(公告)日：2002-12-17
申请号：US09760309
申请日：2001-01-16
申请人： Chrong Jung Lin , Jong Chen , Hung-Der Su , Di-Son Kuo
发明人： Chrong Jung Lin , Jong Chen , Hung-Der Su , Di-Son Kuo
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L29/66825
摘要： A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.
摘要翻译：描述了一种制造具有改进的堆叠栅极拓扑的堆叠栅极闪存EEPROM器件的新方法。在半导体衬底上形成隔离区。隧道氧化物层设置在半导体衬底的表面上。沉积在隧道氧化物层上的第一多晶硅层。将第一多晶硅层抛光直到多晶硅的顶表面平坦并平行于半导体衬底的顶表面。蚀刻掉第一多晶硅层以形成浮栅。源极和漏极区域形成在半导体衬底内。沉积在第一多晶硅层上的多层介电层。第二多晶硅层沉积在叠层电介质层上。蚀刻掉第二多晶硅层和互聚电介质层以形成覆盖浮栅的控制栅极。绝缘层沉积在氧化层和控制栅上。通过绝缘层到底层的控制栅极和底层的源极和漏极区域形成接触开口。接触开口填充有导电层以完成闪速EEPROM装置的制造。

6. 发明授权

US6153494A Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash 有权
标题翻译：通过堆叠栅极闪存中的横向耦合来增加字线与浮动栅极的耦合比的方法
公开(公告)号：US6153494A
公开(公告)日：2000-11-28
申请号：US310257
申请日：1999-05-12
申请人： Chia-Ta Hsieh , Di-Son Kuo , Yai-Fen Lin , Chrong Jung Lin , Jong Chen , Hung-Der Su
发明人： Chia-Ta Hsieh , Di-Son Kuo , Yai-Fen Lin , Chrong Jung Lin , Jong Chen , Hung-Der Su
IPC分类号： H01L21/762 , H01L21/8247 , H01L27/115 , H01L21/76
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： A method is provided for forming a stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling. This is accomplished by first depositing an unconventionally high or thick layer of nitride and then forming a shallow trench isolation (STI) through the nitride layer into the substrate, filling the STI with isolation oxide, removing the nitride thus leaving behind a deep opening about the filled STI, filling conformally the opening with a first polysilicon layer to form a floating gate, forming interpoly oxide layer over the floating gate, and then forming a second polysilicon layer to form the control gate and finally forming the self-aligned source of the stacked-gate flash memory cell of the invention. A stacked-gate flash memory cell is also provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.
摘要翻译：提供一种用于形成具有高阶氧化物和高横向耦合的浅沟槽隔离的堆叠栅极快闪存储器单元的方法。这是通过首先沉积非常规高或较厚的氮化物层，然后通过氮化物层形成浅沟槽隔离（STI）到衬底中，用隔离氧化物填充STI，从而除去氮化物，从而留下围绕填充STI，用第一多晶硅层保形地填充开口以形成浮置栅极，在浮置栅极上形成多晶硅层，然后形成第二多晶硅层以形成控制栅极，并最终形成堆叠的自对准源本发明的闪存单元。还提供了堆叠栅极闪存单元，其具有具有高阶氧化物和高横向耦合的浅沟槽隔离。

7. 发明授权

US6037223A Stack gate flash memory cell featuring symmetric self aligned contact structures 有权
标题翻译：具有对称自对准接触结构的堆栈门闪存单元
公开(公告)号：US6037223A
公开(公告)日：2000-03-14
申请号：US177342
申请日：1998-10-23
申请人： Hung-Der Su , Chrong-Jung Lin , Jong Chen , Di-Son Kuo
发明人： Hung-Der Su , Chrong-Jung Lin , Jong Chen , Di-Son Kuo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A process for fabricating a flash memory cell, featuring self-aligned contact structures, overlying and contacting, self-aligned source, and self-aligned drain regions, located between stack gate structures, has been developed. The stack gate structures, located on an underlying silicon dioxide, tunnel oxide layer, are comprised of: a capping insulator shape; a polysilicon control gate shape; an inter-polysilicon dielectric shape; and a polysilicon floating gate shape. The use of self-aligned contact structures, and self-aligned source regions, allows increased cell densities to be achieved.
摘要翻译：已经开发了一种用于制造闪存单元的方法，其特征在于位于堆叠栅极结构之间的自对准接触结构，覆盖和接触自对准源极和自对准漏极区。位于下面的二氧化硅隧道氧化物层上的堆叠栅极结构包括：封盖绝缘体形状; 多晶硅控制门形状; 多晶硅间介质形状; 和多晶硅浮栅形状。使用自对准接触结构和自对准的源区域可以实现提高的细胞密度。

8. 发明授权

US6001687A Process for forming self-aligned source in flash cell using SiN spacer as hard mask 有权
标题翻译：使用SiN间隔物作为硬掩模在闪存单元中形成自对准源的工艺
公开(公告)号：US6001687A
公开(公告)日：1999-12-14
申请号：US283849
申请日：1999-04-01
申请人： Wen-Ting Chu , Di-Son Kuo , Chrong-Jung Lin , Hung-Der Su , Jong Chen
发明人： Wen-Ting Chu , Di-Son Kuo , Chrong-Jung Lin , Hung-Der Su , Jong Chen
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/8239
CPC分类号： H01L27/11521
摘要： When FLASH cells are made in association with STI (as opposed to LOCOS) it is often the case that stringers of silicon nitride are left behind after the spacers have been formed. This problem has been eliminated by requiring that the oxide in the STI trenches remain in place at the time that the silicon nitride spacers are formed. After that, the oxide is removed in the usual manner, following which a SALICIDE process is used to form a self aligned source line. When this sequence is followed no stringers are left behind on the walls of the trench, guaranteeing the absence of any open circuits or high resistance regions in the source line.
摘要翻译：当与STI（与LOCOS相反）制成FLASH单元时，通常在形成间隔物之后留下氮化硅桁条。通过要求在形成氮化硅间隔物的时刻STI槽中的氧化物保持在适当位置，已经消除了这个问题。之后，以通常的方式去除氧化物，随后使用SALICIDE工艺来形成自对准的源极线。当遵循该顺序时，沟槽的壁上不留下桁条，保证在源极线中不存在任何开路或高电阻区域。

9. 发明授权

US06251744B1 Implant method to improve characteristics of high voltage isolation and high voltage breakdown 有权
标题翻译：植入法提高高压隔离和高压击穿特性
公开(公告)号：US06251744B1
公开(公告)日：2001-06-26
申请号：US09356870
申请日：1999-07-19
申请人： Hung-Der Su , Chrong-Jung Lin , Jong Chen , Wen-Ting Chu , Hung-Cheng Sung , Di-Son Kuo
发明人： Hung-Der Su , Chrong-Jung Lin , Jong Chen , Wen-Ting Chu , Hung-Cheng Sung , Di-Son Kuo
IPC分类号： H01L2176
CPC分类号： H01L21/76213
摘要： A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.
摘要翻译：在半导体衬底的n阱或p阱区域上生长一层良好的氧化物。在高电压器件区域中进行深n阱注入，随后是深n阱注入的深n阱驱动。去除氧化物; 在高电压器件区域中产生场氧化物（FOX）区域。牺牲氧化物层沉积在半导体衬底的表面上。在半导体衬底的高电压PMOS区域中执行低电压簇n阱注入，随后是高压NMOS区，由低电压簇p阱注入，随后是埋置的p阱簇注入。

10. 发明授权

US06190969B1 Method to fabricate a flash memory cell with a planar stacked gate 有权
公开(公告)号：US06190969B1
公开(公告)日：2001-02-20
申请号：US09257722
申请日：1999-02-25
申请人： Chrong Jung Lin , Jong Chen , Hung-Der Su , Di-Son Kuo
发明人： Chrong Jung Lin , Jong Chen , Hung-Der Su , Di-Son Kuo
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L29/66825
摘要： A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.

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