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1. 发明授权

US07765498B1 Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist 有权
标题翻译：将过程引起的布局维度变化纳入集成电路仿真网表的方法
公开(公告)号：US07765498B1
公开(公告)日：2010-07-27
申请号：US11805739
申请日：2007-05-24
申请人： Jonathan J. Ho , Yan Wang , Xin X. Wu , Jane W. Sowards
发明人： Jonathan J. Ho , Yan Wang , Xin X. Wu , Jane W. Sowards
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5081
摘要： Computer-implemented methods of generating netlists for use in post-layout simulation procedures. A lookup table includes a predetermined set of features (e.g., transistors of specified sizes and shapes) supported by an integrated circuit (IC) fabrication process, with dimensions and process induced dimension variations being included for each feature. A netlist is extracted from an IC layout, the extracted netlist specifying circuit elements (e.g., transistors) implemented by the IC layout and interconnections between the circuit elements. A search pattern is run on the IC layout to identify features in the IC layout corresponding to features included in the lookup table. Circuit elements in the extracted netlist that correspond to the identified features are then modified using values from the lookup table, and the modified netlist is output. In some embodiments, the netlist extraction, search pattern, and netlist modification are all performed as a single netlist generation step.
摘要翻译：计算机实现的生成用于后布局模拟程序的网表的方法。查找表包括由集成电路（IC）制造过程支持的预定的一组特征（例如，特定尺寸和形状的晶体管），其中每个特征包括尺寸和工艺引起的尺寸变化。从IC布局提取网表，提取的网表指定电路元件（例如，晶体管）由IC布局实现，并且电路元件之间的互连。在IC布局上运行搜索模式，以识别与查找表中包含的功能相对应的IC布局中的功能。然后使用来自查找表的值来修改对应于所识别的特征的提取的网表中的电路元件，并输出修改的网表。在一些实施例中，网表提取，搜索模式和网表修改都被执行为单个网表生成步骤。

2. 发明授权

US06868537B1 Method of generating an IC mask using a reduced database 有权
标题翻译：使用简化数据库生成IC掩模的方法
公开(公告)号：US06868537B1
公开(公告)日：2005-03-15
申请号：US10082991
申请日：2002-02-25
申请人： Jonathan J. Ho , Xin X. Wu , Zicheng Gary Ling , Jan L. de Jong
发明人： Jonathan J. Ho , Xin X. Wu , Zicheng Gary Ling , Jan L. de Jong
IPC分类号： G03F1/14 , G06F17/50
CPC分类号： G03F1/36 , G03F1/68 , G06F17/5068 , G06F2217/12
摘要： For IC devices that have repeating structures, a method of generating a database for making a mask layer starts with a hierarchical database describing at least one repeating element in the layer, a skeleton that surrounds the repeating elements, and instructions as to where to locate the repeating elements within the skeleton. This database is modified to generate a database that has optical proximity correction (OPC) for diffraction of light that will pass through the mask and expose photoresist on the IC layer. The optical-proximity corrected mask database is fractured by a mask house using instructions on how the modified data base will be divided to form repeating elements that are still identical after OPC, a mask skeleton that includes non-repeating elements, and instructions for placement of the repeating elements in the skeleton. Thus the resulting mask database is smaller than a mask database that includes all copies of repeating elements.
摘要翻译：对于具有重复结构的IC设备，生成用于制作掩模层的数据库的方法从描述层中的至少一个重复元素的分层数据库开始，围绕重复元素的骨架以及关于在哪里定位的指令重复骨骼内的元素。该数据库被修改以产生具有光学邻近校正（OPC）的数据库，用于衍射通过掩模并在IC层上曝光光致抗蚀剂的光的衍射。使用关于如何将经修改的数据库分割以形成在OPC之后仍然相同的重复元素的指令，包含非重复元素的掩码框架以及用于放置骨骼中的重复元素。因此，所得到的掩码数据库小于包含所有重复元素副本的掩码数据库。

3. 发明授权

US06569584B1 Methods and structures for protecting reticles from electrostatic damage 失效
标题翻译：保护掩模版免受静电损伤的方法和结构
公开(公告)号：US06569584B1
公开(公告)日：2003-05-27
申请号：US09895538
申请日：2001-06-29
申请人： Jonathan J. Ho , Xin X. Wu
发明人： Jonathan J. Ho , Xin X. Wu
IPC分类号： G03F900
CPC分类号： G03F1/40
摘要： A reticle (mask) that is modified to prevent bridging of the masking material (e.g., chrome) between long mask lines of a lithographic mask pattern during an integrated circuit fabrication process. A dummy mask pattern is provided on the reticle adjacent to long mask lines that causes the large charge collected on the long mask line to be distributed along its length, thereby minimizing voltage potentials across a gap separating the long mask line from an adjacent mask line.
摘要翻译：在集成电路制造工艺期间，被修改以防止掩模材料（例如，铬）在光刻掩模图案的长掩模线之间桥接的掩模版（掩模）。伪掩模图案设置在与长掩模线相邻的掩模版上，使得长长掩模线上收集的大电荷沿其长度分布，从而使隔离长掩模线与相邻掩模线的间隙的电压电位最小化。

4. 发明授权

US07673270B1 Method and apparatus for compensating an integrated circuit layout for mechanical stress effects 有权
标题翻译：用于补偿机械应力影响的集成电路布局的方法和装置
公开(公告)号：US07673270B1
公开(公告)日：2010-03-02
申请号：US11717811
申请日：2007-03-13
申请人： Yan Wang , Nui Chong , Hong-Tsz Pan , Bang-Thu Nguyen , Jonathan Jung-Ching Ho , Qi Lin , Yuhao Luo , Hing Yee Angela Wong , Xin X. Wu , Yuezhen Fan
发明人： Yan Wang , Nui Chong , Hong-Tsz Pan , Bang-Thu Nguyen , Jonathan Jung-Ching Ho , Qi Lin , Yuhao Luo , Hing Yee Angela Wong , Xin X. Wu , Yuezhen Fan
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Method and apparatus for compensating an integrated circuit design for mechanical stress effects. One aspect of the invention relates to designing an integrated circuit. Layout data is obtained that describes layers of the integrated circuit. At least one of the layers is analyzed to detect at least one structure susceptible to damage from mechanical stress. A bias is automatically added to each of the at least one structure to reduce mechanical stress of the at least one structure as fabricated. Augmented layout data is then provided for the integrated circuit.
摘要翻译：用于补偿机械应力作用的集成电路设计的方法和装置。本发明的一个方面涉及集成电路的设计。获得描述集成电路层的布局数据。分析至少一层以检测易受机械应力破坏的至少一种结构。偏置被自动地添加到至少一个结构中的每个结构中，以减少所制造的至少一个结构的机械应力。然后为集成电路提供增强的布局数据。

5. 发明授权

US07956385B1 Circuit for protecting a transistor during the manufacture of an integrated circuit device 有权
标题翻译：用于在制造集成电路器件期间保护晶体管的电路
公开(公告)号：US07956385B1
公开(公告)日：2011-06-07
申请号：US12847957
申请日：2010-07-30
申请人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak K. Nayak , Daniel Gitlin
发明人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak K. Nayak , Daniel Gitlin
IPC分类号： H01L23/525
CPC分类号： H01L27/0251
摘要： A circuit for protecting a transistor during the manufacture of an integrated circuit device is disclosed. The circuit comprises a transistor having a gate formed over an active region formed in a die of the integrated circuit device; a protection element formed in the die of the integrated circuit device; and a programmable interconnect coupled between the gate of the transistor and the protection element, the programmable interconnect enabling the protection element to be decoupled from the transistor.
摘要翻译：公开了一种用于在制造集成电路器件期间保护晶体管的电路。该电路包括晶体管，其晶体管具有形成在集成电路器件的管芯中的有源区上的栅极; 形成在集成电路器件的管芯中的保护元件; 以及耦合在所述晶体管的栅极和所述保护元件之间的可编程互连，所述可编程互连使得所述保护元件能够与所述晶体管分离。

6. 发明授权

US07772093B2 Method of and circuit for protecting a transistor formed on a die 有权
标题翻译：用于保护形成在管芯上的晶体管的方法和电路
公开(公告)号：US07772093B2
公开(公告)日：2010-08-10
申请号：US11977810
申请日：2007-10-26
申请人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak Kumar Nayak , Daniel Gitlin
发明人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak Kumar Nayak , Daniel Gitlin
IPC分类号： H01L21/326 , H01L21/479
CPC分类号： H01L27/0251
摘要： A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.
摘要翻译：公开了一种保护形成在集成电路的管芯上的晶体管的方法。该方法包括在晶片上形成晶体管的有源区; 在有源区上形成晶体管的栅极; 将初级接触耦合到晶体管的栅极; 在所述晶体管的栅极和保护元件之间耦合可编程元件; 以及通过可编程元件将保护元件与晶体管的栅极去耦合。还公开了用于保护形成在集成电路的管芯上的晶体管的电路。

7. 发明授权

US06376131B1 Methods and structures for protecting reticles from ESD failure 失效
标题翻译：保护掩模版免受ESD故障的方法和结构
公开(公告)号：US06376131B1
公开(公告)日：2002-04-23
申请号：US09542127
申请日：2000-04-04
申请人： Jae Cho , Zhi-Min Ling , Xin X. Wu
发明人： Jae Cho , Zhi-Min Ling , Xin X. Wu
IPC分类号： G03F900
CPC分类号： G03F1/40
摘要： A reticle that is modified to prevent bridging of the masking material (e.g., chrome) between portions of the lithographic mask pattern during an integrated circuit fabrication process. According to a first aspect, the modification involves electrically connecting the various portions of the lithographic mask pattern that balance charges generated in the portions during fabrication processes. In one embodiment, sub-resolution wires that extend between the lithographic mask pattern portions facilitate electrical conduction between the mask pattern portions, thereby equalizing dissimilar charges. In another embodiment, a transparent conductive film is formed over the lithographic mask pattern to facilitate conduction. In accordance with a second aspect, the modification involves separating the various portions of the lithographic mask pattern into relatively small segments by providing sub-resolution gaps between the various portions, thereby minimizing the amount of charge that is generated on each portion.
摘要翻译：在集成电路制造工艺期间，被修饰以防止掩模材料（例如，铬）桥接在光刻掩模图案的部分之间的掩模版。根据第一方面，修改涉及电连接平版印刷掩模图案的各个部分，以平衡在制造工艺期间部分中产生的电荷。在一个实施例中，在光刻掩模图案部分之间延伸的子分辨率线促进掩模图案部分之间的导电，从而均衡不同的电荷。在另一个实施例中，在光刻掩模图案之上形成透明导电膜以促进传导。根据第二方面，修改包括通过在各部分之间提供次分辨率间隙将光刻掩模图案的各个部分分离成相对较小的部分，从而最小化在每个部分上产生的电荷量。

8. 发明授权

US07737439B2 Semiconductor component having test pads and method and apparatus for testing same 有权
标题翻译：具有测试焊盘的半导体部件及其测试方法和装置
公开(公告)号：US07737439B2
公开(公告)日：2010-06-15
申请号：US11804391
申请日：2007-05-17
申请人： Mohsen Hossein Mardi , Jae Cho , Xin X. Wu , Chih-Chung Wu , Shih-Liang Liang , Sanjiv Stokes , Hassan K. Bazargan
发明人： Mohsen Hossein Mardi , Jae Cho , Xin X. Wu , Chih-Chung Wu , Shih-Liang Liang , Sanjiv Stokes , Hassan K. Bazargan
IPC分类号： H01L23/485
CPC分类号： H01L22/32 , H01L24/05 , H01L24/06 , H01L2224/02166 , H01L2224/0401 , H01L2224/05552 , H01L2224/05554 , H01L2224/05567 , H01L2224/05599 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K1/0268 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads.
摘要翻译：描述了具有测试焊盘的半导体部件及其测试方法和装置。在一个示例中，获得具有被配置为支撑凸起的触点和多个测试焊盘的接合焊盘图案的未凸起的衬底。多个测试焊盘中的每一个与相应的一个接合焊盘电连通。使用多个测试垫测试衬底。在另一示例中，制造具有被配置为支撑凸起的触点和多个测试焊盘的接合焊盘图案的衬底。多个测试焊盘中的每一个与相应的一个接合焊盘电连通。使用多个测试垫测试衬底。绝缘层形成在多个测试焊盘上。

9. 发明申请

US20090108337A1 Method of and circuit for protecting a transistor formed on a die 有权
标题翻译：用于保护形成在管芯上的晶体管的方法和电路
公开(公告)号：US20090108337A1
公开(公告)日：2009-04-30
申请号：US11977810
申请日：2007-10-26
申请人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak Kumar Nayak , Daniel Gitlin
发明人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak Kumar Nayak , Daniel Gitlin
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L27/0251
摘要： A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.
摘要翻译：公开了一种保护形成在集成电路的管芯上的晶体管的方法。该方法包括在晶片上形成晶体管的有源区; 在有源区上形成晶体管的栅极; 将初级接触耦合到晶体管的栅极; 在所述晶体管的栅极和保护元件之间耦合可编程元件; 以及通过可编程元件将保护元件与晶体管的栅极去耦合。还公开了用于保护形成在集成电路的管芯上的晶体管的电路。

10. 发明授权

US06645802B1 Method of forming a zener diode 有权
标题翻译：形成齐纳二极管的方法
公开(公告)号：US06645802B1
公开(公告)日：2003-11-11
申请号：US09877690
申请日：2001-06-08
申请人： Sheau-Suey Li , Shahin Toutounchi , Michael J. Hart , Xin X. Wu , Daniel Gitlin
发明人： Sheau-Suey Li , Shahin Toutounchi , Michael J. Hart , Xin X. Wu , Daniel Gitlin
IPC分类号： H01L218234
CPC分类号： H01L27/0251 , Y10S438/983
摘要： An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.
摘要翻译： ESD保护电路包括形成在半导体衬底上和半导体衬底内的双极晶体管，电阻器和齐纳二极管。电阻器在晶体管的基极和发射极区域之间延伸，使跨越电阻器的电压可以导通晶体管。齐纳二极管与电阻器串联形成，并在晶体管的基极和集电极区域之间延伸。如此配置，通常通过齐纳二极管的击穿电流（通常响应于ESD事件）导通晶体管，以为ESD提供非破坏性的放电路径。齐纳二极管包括阳极和阴极扩散。阴极扩散沿垂直于衬底的方向向下延伸到半导体衬底中。阳极扩散通过阴极扩散向下延伸到半导体衬底中。阳极扩散比阴极扩散向下延伸，使得齐纳二极管相对于衬底垂直布置。可以使用两个分开的扩散形成阴极扩散，其中一个扩散比其它扩散更深。

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