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1. 发明授权

US06868537B1 Method of generating an IC mask using a reduced database 有权
标题翻译：使用简化数据库生成IC掩模的方法
公开(公告)号：US06868537B1
公开(公告)日：2005-03-15
申请号：US10082991
申请日：2002-02-25
申请人： Jonathan J. Ho , Xin X. Wu , Zicheng Gary Ling , Jan L. de Jong
发明人： Jonathan J. Ho , Xin X. Wu , Zicheng Gary Ling , Jan L. de Jong
IPC分类号： G03F1/14 , G06F17/50
CPC分类号： G03F1/36 , G03F1/68 , G06F17/5068 , G06F2217/12
摘要： For IC devices that have repeating structures, a method of generating a database for making a mask layer starts with a hierarchical database describing at least one repeating element in the layer, a skeleton that surrounds the repeating elements, and instructions as to where to locate the repeating elements within the skeleton. This database is modified to generate a database that has optical proximity correction (OPC) for diffraction of light that will pass through the mask and expose photoresist on the IC layer. The optical-proximity corrected mask database is fractured by a mask house using instructions on how the modified data base will be divided to form repeating elements that are still identical after OPC, a mask skeleton that includes non-repeating elements, and instructions for placement of the repeating elements in the skeleton. Thus the resulting mask database is smaller than a mask database that includes all copies of repeating elements.
摘要翻译：对于具有重复结构的IC设备，生成用于制作掩模层的数据库的方法从描述层中的至少一个重复元素的分层数据库开始，围绕重复元素的骨架以及关于在哪里定位的指令重复骨骼内的元素。该数据库被修改以产生具有光学邻近校正（OPC）的数据库，用于衍射通过掩模并在IC层上曝光光致抗蚀剂的光的衍射。使用关于如何将经修改的数据库分割以形成在OPC之后仍然相同的重复元素的指令，包含非重复元素的掩码框架以及用于放置骨骼中的重复元素。因此，所得到的掩码数据库小于包含所有重复元素副本的掩码数据库。

2. 发明授权

US07765498B1 Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlist 有权
标题翻译：将过程引起的布局维度变化纳入集成电路仿真网表的方法
公开(公告)号：US07765498B1
公开(公告)日：2010-07-27
申请号：US11805739
申请日：2007-05-24
申请人： Jonathan J. Ho , Yan Wang , Xin X. Wu , Jane W. Sowards
发明人： Jonathan J. Ho , Yan Wang , Xin X. Wu , Jane W. Sowards
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5081
摘要： Computer-implemented methods of generating netlists for use in post-layout simulation procedures. A lookup table includes a predetermined set of features (e.g., transistors of specified sizes and shapes) supported by an integrated circuit (IC) fabrication process, with dimensions and process induced dimension variations being included for each feature. A netlist is extracted from an IC layout, the extracted netlist specifying circuit elements (e.g., transistors) implemented by the IC layout and interconnections between the circuit elements. A search pattern is run on the IC layout to identify features in the IC layout corresponding to features included in the lookup table. Circuit elements in the extracted netlist that correspond to the identified features are then modified using values from the lookup table, and the modified netlist is output. In some embodiments, the netlist extraction, search pattern, and netlist modification are all performed as a single netlist generation step.
摘要翻译：计算机实现的生成用于后布局模拟程序的网表的方法。查找表包括由集成电路（IC）制造过程支持的预定的一组特征（例如，特定尺寸和形状的晶体管），其中每个特征包括尺寸和工艺引起的尺寸变化。从IC布局提取网表，提取的网表指定电路元件（例如，晶体管）由IC布局实现，并且电路元件之间的互连。在IC布局上运行搜索模式，以识别与查找表中包含的功能相对应的IC布局中的功能。然后使用来自查找表的值来修改对应于所识别的特征的提取的网表中的电路元件，并输出修改的网表。在一些实施例中，网表提取，搜索模式和网表修改都被执行为单个网表生成步骤。

3. 发明授权

US06569584B1 Methods and structures for protecting reticles from electrostatic damage 失效
标题翻译：保护掩模版免受静电损伤的方法和结构
公开(公告)号：US06569584B1
公开(公告)日：2003-05-27
申请号：US09895538
申请日：2001-06-29
申请人： Jonathan J. Ho , Xin X. Wu
发明人： Jonathan J. Ho , Xin X. Wu
IPC分类号： G03F900
CPC分类号： G03F1/40
摘要： A reticle (mask) that is modified to prevent bridging of the masking material (e.g., chrome) between long mask lines of a lithographic mask pattern during an integrated circuit fabrication process. A dummy mask pattern is provided on the reticle adjacent to long mask lines that causes the large charge collected on the long mask line to be distributed along its length, thereby minimizing voltage potentials across a gap separating the long mask line from an adjacent mask line.
摘要翻译：在集成电路制造工艺期间，被修改以防止掩模材料（例如，铬）在光刻掩模图案的长掩模线之间桥接的掩模版（掩模）。伪掩模图案设置在与长掩模线相邻的掩模版上，使得长长掩模线上收集的大电荷沿其长度分布，从而使隔离长掩模线与相邻掩模线的间隙的电压电位最小化。

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