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1. 发明授权

US07636653B1 Point-to-point ethernet hardware co-simulation interface 有权
标题翻译：点到点以太网硬件协同仿真界面
公开(公告)号：US07636653B1
公开(公告)日：2009-12-22
申请号：US11343367
申请日：2006-01-31
申请人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi , Roger B. Milne
发明人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi , Roger B. Milne
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5027
摘要： An Ethernet co-simulation interface for use with a software-based simulation tool and a design under test disposed on a programmable device can include a host interface and a network processor. The host interface can execute on a host computing system and facilitate data transfer between the software-based simulation tool and a communication link to the design under test. The network processor can be implemented within the programmable device and facilitate data transfer between the communication link and the design under test. The host interface and the network processor can exchange simulation data formatted as raw Ethernet frames over a point-to-point Ethernet connection.
摘要翻译：与可编程设备上的基于软件的仿真工具和被测设计一起使用的以太网协同仿真界面可以包括主机接口和网络处理器。主机接口可以在主机计算系统上执行，并促进基于软件的仿真工具与被测设计的通信链路之间的数据传输。网络处理器可以在可编程设备内部实现，并促进通信链路和被测设计之间的数据传输。主机接口和网络处理器可以通过点对点以太网连接交换格式化为原始以太网帧的模拟数据。

2. 发明授权

US07707019B1 Command buffering for hardware co-simulation 有权
标题翻译：用于硬件协同仿真的命令缓冲
公开(公告)号：US07707019B1
公开(公告)日：2010-04-27
申请号：US11234529
申请日：2005-09-23
申请人： Jonathan B. Ballagh , Chi Bun Chan , Nabeel Shirazi , Roger B. Milne
发明人： Jonathan B. Ballagh , Chi Bun Chan , Nabeel Shirazi , Roger B. Milne
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： A method of co-simulation involving a high level modeling system and an integrated circuit such as, e.g., a programmable logic device (PLD) can include, when writing to at least one input port of the PLD, storing a plurality of commands from a co-simulation engine within a command buffer and, responsive to a send condition, sending the plurality of commands to the PLD as a single transaction. When reading from at least one output port of the PLD, selectively reading from a cache external to the PLD or a memory of the PLD according to a state of cache coherency.
摘要翻译：涉及高级建模系统和诸如可编程逻辑器件（PLD）的集成电路的协同仿真的方法可以包括在写入PLD的至少一个输入端口时存储来自协同仿真引擎，并且响应于发送条件，将多个命令作为单个事务发送到PLD。当从PLD的至少一个输出端口读取时，根据高速缓存一致性的状态选择性地从PLD外部的高速缓存或PLD的存储器读取。

3. 发明授权

US08224638B1 Managing programmable device configuration 有权
标题翻译：管理可编程器件配置
公开(公告)号：US08224638B1
公开(公告)日：2012-07-17
申请号：US11650176
申请日：2007-01-05
申请人： Nabeel Shirazi , Chi Bun Chan , Bradley K. Fross , Shay Ping Seng , Jonathan B. Ballagh
发明人： Nabeel Shirazi , Chi Bun Chan , Bradley K. Fross , Shay Ping Seng , Jonathan B. Ballagh
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5054 , G06F2213/0038
摘要： A method of managing programmable device configuration can include running a server configuration image within the programmable device and storing a different configuration image within a non-volatile memory communicatively linked with the programmable device. Responsive to a switch request sent from the client to the programmable device over the communications link, the different configuration image can be loaded into the programmable device.
摘要翻译：管理可编程设备配置的方法可以包括在可编程设备内运行服务器配置图像并将不同的配置图像存储在与可编程设备通信地链接的非易失性存储器中。响应于通过通信链路从客户端发送到可编程设备的切换请求，可以将不同的配置图像加载到可编程设备中。

4. 发明授权

US07747423B1 Systems and methods of co-simulation utilizing multiple PLDs in a boundary scan chain 有权
标题翻译：在边界扫描链中利用多个PLD进行协同仿真的系统和方法
公开(公告)号：US07747423B1
公开(公告)日：2010-06-29
申请号：US11527841
申请日：2006-09-27
申请人： Nabeel Shirazi , Jonathan B. Ballagh , Chi Bun Chan
发明人： Nabeel Shirazi , Jonathan B. Ballagh , Chi Bun Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： Systems and methods of performing co-simulation of a partitioned circuit design using multiple programmable logic devices (PLDs) coupled together to form a boundary scan chain. A host computer is coupled to the scan chain via a programming cable. Resident on the host computer are run-time co-simulation blocks corresponding to blocks from the circuit design, where each block is designated to run on one of the PLDs in the scan chain; a programming cable device driver interfacing with the programming cable; and a proxy component. The proxy component is coupled to all of the run-time co-simulation blocks and the programming cable device driver. Each co-simulation block includes a unique pattern identifier, which is also present in the associated PLD. Using this pattern identifier, data and commands targeted to a specific PLD can be extracted from the scan chain, while ignoring data and commands targeted to other PLDs in the scan chain.
摘要翻译：使用耦合在一起以形成边界扫描链的多个可编程逻辑器件（PLD）执行分割电路设计的协同仿真的系统和方法。主机通过编程电缆耦合到扫描链。主计算机上的驻留是与电路设计中的块对应的运行时协同仿真块，其中每个块被指定为在扫描链中的一个PLD上运行; 与编程电缆接口的编程电缆设备驱动器; 和代理组件。代理组件耦合到所有运行时协同仿真模块和编程电缆设备驱动程序。每个共模拟块包括唯一的模式标识符，其也存在于相关联的PLD中。使用此模式标识符，可以从扫描链中提取针对特定PLD的数据和命令，同时忽略针对扫描链中其他PLD的数据和命令。

5. 发明授权

US08812289B1 Simulation that transfers port values of a design block via a configuration block of a programmable device 有权
标题翻译：模拟通过可编程设备的配置块传输设计块的端口值
公开(公告)号：US08812289B1
公开(公告)日：2014-08-19
申请号：US11732642
申请日：2007-04-04
申请人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
发明人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
IPC分类号： G06F9/455 , G06F17/50 , G06F11/36 , G06F17/22 , G06F11/267
CPC分类号： G06F17/5027 , G06F9/455 , G06F11/267 , G06F11/3652 , G06F17/22 , G06F17/5009 , G06F2217/86
摘要： Approaches for simulating an electronic system. In one approach, a software co-simulation platform is configured to produce a first time sequence of values of a plurality of input ports of a design block of the electronic system, consume a second time sequence of values of a plurality of output ports of the design block, and generate access transactions for transferring the first and second sequences of values. The software co-simulation platform generates a plurality of reconfiguration transactions for transferring reconfiguration data for the design block. A PLD is configured to implement a communication block and a control block. The communication block receives the reconfiguration and access transactions from the software co-simulation platform, and the control block reconfigures programmable logic and interconnect resources of the PLD in response to the reconfiguration transactions. The control block also controls the emulation of the design block in response to the access transactions.
摘要翻译：模拟电子系统的方法。在一种方法中，软件协同仿真平台被配置为产生电子系统的设计块的多个输入端口的值的第一时间序列，消耗电子系统的多个输出端口的值的第二时间序列并且生成用于传送第一和第二序列值的访问事务。软件协同仿真平台生成用于传送用于设计块的重新配置数据的多个重配置事务。 PLD被配置为实现通信块和控制块。通信块从软件协同仿真平台接收重新配置和访问事务，并且控制块响应于重新配置事务重新配置PLD的可编程逻辑和互连资源。响应于访问事务，控制块还控制设计块的仿真。

6. 发明授权

US07590137B1 Parameterizable compact network processor for low-level communication with an integrated circuit 有权
标题翻译：可配置的紧凑型网络处理器，用于与集成电路进行低级通信
公开(公告)号：US07590137B1
公开(公告)日：2009-09-15
申请号：US11285708
申请日：2005-11-22
申请人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
发明人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
IPC分类号： H04J3/24
CPC分类号： G06F13/385 , G06F2213/3808
摘要： A network processor, disposed on an integrated circuit can include an ingress unit having a dual port block random access memory and an egress unit having a dual port block random access memory. The network processor further can include a network interface configured to write packetized data to the ingress unit and read packetized data from the egress unit as well as a coordination processor configured to coordinate movement of data between the network interface, the ingress unit, and the egress unit.
摘要翻译：设置在集成电路上的网络处理器可以包括具有双端口块随机存取存储器的入口单元和具有双端口块随机存取存储器的出口单元。网络处理器还可以包括被配置为将分组化数据写入入口单元并从出口单元读取分组化数据的网络接口以及配置为协调网络接口，入口单元和出口之间的数据移动的协调处理器单元。

7. 发明授权

US07346482B1 Shared memory for co-simulation 有权
标题翻译：共享内存共同模拟
公开(公告)号：US07346482B1
公开(公告)日：2008-03-18
申请号：US11075340
申请日：2005-03-08
申请人： Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi , Joshua Ian Stone
发明人： Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi , Joshua Ian Stone
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Co-simulation of a circuit design includes simulating a first subset of blocks of the circuit design on a software-based co-simulation platform, simulating a second subset of the blocks of the circuit design on a hardware-based co-simulation platform, and maintaining coherency for a memory block of the circuit design between a first representation of data in the memory block on the software-based co-simulation platform and a second representation of the data in the memory block on the hardware-based co-simulation platform. Coherency is maintained by managing mutually exclusive access to the memory block from the first subset of blocks and the second subset of blocks.
摘要翻译：电路设计的协同仿真包括在基于软件的协同仿真平台上模拟电路设计的块的第一子集，在基于硬件的协同仿真平台上模拟电路设计的块的第二子集，以及在基于软件的协同仿真平台的存储器块中的数据的第一表示和基于硬件的协同仿真平台的存储器块中的数据的第二表示之间维持电路设计的存储器块的一致性。通过管理来自块的第一子集和块的第二子集的对存储器块的互斥访问来维持一致性。

8. 发明授权

US07343572B1 Vector interface to shared memory in simulating a circuit design 有权
标题翻译：模拟电路设计的共享内存的矢量接口
公开(公告)号：US07343572B1
公开(公告)日：2008-03-11
申请号：US11096024
申请日：2005-03-31
申请人： Joshua Ian Stone , Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi
发明人： Joshua Ian Stone , Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A first block, a second block, a shared memory, and a third block are generated in a circuit design in response to user input control. The first block is coupled to the second block, the second block is coupled to the shared memory, and the shared memory is coupled to the third block in response to user input control. During one cycle of a simulation, the second block, in response to the first block, accesses a set of scalar values in the shared memory using scalar accesses. During one cycle of the simulation, the set of scalar values is transferred between the second block and the first block. During the simulation, the shared memory is accessed by the third block using scalar accesses.
摘要翻译：响应于用户输入控制，在电路设计中产生第一块，第二块，共享存储器和第三块。第一块耦合到第二块，第二块耦合到共享存储器，并且响应于用户输入控制，共享存储器耦合到第三块。在仿真的一个周期期间，响应于第一个块，第二个块使用标量访问访问共享存储器中的一组标量值。在模拟的一个周期期间，标量值集合在第二块和第一块之间传送。在仿真期间，使用标量访问由第三块访问共享存储器。

9. 发明授权

US07003751B1 Specification of the hierarchy, connectivity, and graphical representation of a circuit design 有权
标题翻译：电路设计的层次结构，连接性和图形表示的规范
公开(公告)号：US07003751B1
公开(公告)日：2006-02-21
申请号：US10340498
申请日：2003-01-10
申请人： Jeffrey D. Stroomer , Roger B. Milne , Jonathan B. Ballagh , Haibing Ma , L. James Hwang , Nabeel Shirazi
发明人： Jeffrey D. Stroomer , Roger B. Milne , Jonathan B. Ballagh , Haibing Ma , L. James Hwang , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Method and apparatus for creating a circuit design. An object-oriented program instantiates a plurality of objects that model a circuit design. The objects have hierarchy attributes, connectivity attributes, and display attributes that describe a plurality of modules. The hierarchy attributes define parent-child relationships between modules, the connectivity attributes define input-output connections between modules, and the display attributes define a layout of the modules for viewing. Each of the objects has an associated method for generating a design specification in a selected format. When the program is executed, the design specification is generated from the set of objects. Depending on the capabilities of the available tools, the modules and logic elements are displayed in accordance with the display attributes either from the object-oriented program or from the design specification.
摘要翻译：用于创建电路设计的方法和装置。面向对象的程序实例化建模电路设计的多个对象。对象具有描述多个模块的层次属性，连接属性和显示属性。层次结构属性定义模块之间的父子关系，连接属性定义模块之间的输入输出连接，显示属性定义模块的布局以供查看。每个对象具有用于以所选格式生成设计规范的关联方法。当执行程序时，设计规范是从对象集合生成的。根据可用工具的功能，根据面向对象程序或设计规范的显示属性显示模块和逻辑元素。

10. 发明授权

US07478030B1 Clock stabilization detection for hardware simulation 有权
标题翻译：硬件仿真的时钟稳定检测
公开(公告)号：US07478030B1
公开(公告)日：2009-01-13
申请号：US10600848
申请日：2003-06-19
申请人： Jonathan B. Ballagh , Roger B. Milne , Jeffrey D. Stroomer , L. James Hwang , Nabeel Shirazi
发明人： Jonathan B. Ballagh , Roger B. Milne , Jeffrey D. Stroomer , L. James Hwang , Nabeel Shirazi
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5027 , G06F2217/62
摘要： Method and apparatus for clock stabilization detection for hardware simulation is described. More particularly, a lock signal is obtained, for example from a digital clock module. A least common multiple (LCM) clock signal is generated, for example from a clock module. A control signal is generated at least partially responsive to the LCM clock signal and the lock signal. The control signal may be generated from a state machine and applied to select circuitry, where the control signal is used to mask application of the output clock signal responsive to the control signal.
摘要翻译：描述了用于硬件模拟的时钟稳定检测的方法和装置。更具体地，例如从数字时钟模块获得锁定信号。例如从时钟模块产生最小公共多（LCM）时钟信号。至少部分地响应于LCM时钟信号和锁定信号产生控制信号。控制信号可以从状态机产生并应用于选择电路，其中控制信号用于响应于控制信号屏蔽输出时钟信号的应用。

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