专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08265917B1 Co-simulation synchronization interface for IC modeling 有权
标题翻译：用于IC建模的协同仿真同步接口
公开(公告)号：US08265917B1
公开(公告)日：2012-09-11
申请号：US12036895
申请日：2008-02-25
申请人： Jingzhao Ou , Shay Ping Seng
发明人： Jingzhao Ou , Shay Ping Seng
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022 , G06F17/5054
摘要： A high-level integrated circuit (“IC”) modeling system (400) includes a first co-simulator (418) modeling a first portion of an IC system and a second co-simulator (419) modeling a second portion of the IC system, each co-simulator operating according to initial simulation operating conditions (426). A co-simulation synchronization interface (424) is configured to automatically change at least one of the initial simulation operating conditions to a triggered operating condition (428) in response to a user-selected triggering signal.
摘要翻译：高级集成电路（“IC”）建模系统（400）包括对IC系统的第一部分建模的第一协同仿真器（418）和对IC系统的第二部分建模的第二协同仿真器（419），每个共模拟器根据初始模拟操作条件进行操作（426）。协同仿真同步接口（424）被配置为响应于用户选择的触发信号自动地将初始模拟操作条件中的至少一个改变到触发的操作条件（428）。

2. 发明授权

US08224638B1 Managing programmable device configuration 有权
标题翻译：管理可编程器件配置
公开(公告)号：US08224638B1
公开(公告)日：2012-07-17
申请号：US11650176
申请日：2007-01-05
申请人： Nabeel Shirazi , Chi Bun Chan , Bradley K. Fross , Shay Ping Seng , Jonathan B. Ballagh
发明人： Nabeel Shirazi , Chi Bun Chan , Bradley K. Fross , Shay Ping Seng , Jonathan B. Ballagh
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5054 , G06F2213/0038
摘要： A method of managing programmable device configuration can include running a server configuration image within the programmable device and storing a different configuration image within a non-volatile memory communicatively linked with the programmable device. Responsive to a switch request sent from the client to the programmable device over the communications link, the different configuration image can be loaded into the programmable device.
摘要翻译：管理可编程设备配置的方法可以包括在可编程设备内运行服务器配置图像并将不同的配置图像存储在与可编程设备通信地链接的非易失性存储器中。响应于通过通信链路从客户端发送到可编程设备的切换请求，可以将不同的配置图像加载到可编程设备中。

3. 发明授权

US07617471B1 Processor event interface for programmable integrated circuit based circuit designs 有权
标题翻译：基于可编程集成电路的电路设计的处理器事件接口
公开(公告)号：US07617471B1
公开(公告)日：2009-11-10
申请号：US11714041
申请日：2007-03-05
申请人： Shay Ping Seng , William Edward Allaire , Paul Travis Mobbs , Jing Zhao Ou
发明人： Shay Ping Seng , William Edward Allaire , Paul Travis Mobbs , Jing Zhao Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A method of implementing a circuit design on a programmable integrated circuit can include displaying a list of at least one memory of the circuit design that is associated with the processor. A plurality of attributes of an event for the processor can be received. The plurality of attributes can specify a condition that, when met within at least one memory from the list, causes a signal to be generated to the processor. A description of an event interface for the processor can be automatically created according to the plurality of attributes of the interrupt. The description of the event interface can be incorporated into a description of the circuit design.
摘要翻译：在可编程集成电路上实现电路设计的方法可以包括显示与处理器相关联的电路设计的至少一个存储器的列表。可以接收处理器的事件的多个属性。多个属性可以指定当从列表中的至少一个存储器中满足时，使得向处理器生成信号的条件。可以根据中断的多个属性自动创建处理器事件接口的描述。事件接口的描述可以被合并到电路设计的描述中。

4. 发明授权

US07571395B1 Generation of a circuit design from a command language specification of blocks in matrix form 有权
标题翻译：从矩阵形式的块的命令语言规范生成电路设计
公开(公告)号：US07571395B1
公开(公告)日：2009-08-04
申请号：US11196174
申请日：2005-08-03
申请人： Shay Ping Seng , Arvind Sundararajan
发明人： Shay Ping Seng , Arvind Sundararajan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Generation of a circuit design using a command language. The various approaches include generating in a memory arrangement respective instances of design blocks in response to user-entered commands that specify creation of the instances. Matrix-relative positions of the instances of design blocks are established in the memory arrangement in response to at least one user-entered command that specifies respective matrix positions of the instances. Representative connections between the instances are generated in the memory arrangement in response to a user-entered command having no specification of the connections.
摘要翻译：使用命令语言生成电路设计。各种方法包括响应于指定实例的创建的用户输入的命令，在存储器布置中生成设计块的各个实例。响应于指定实例的各个矩阵位置的至少一个用户输入的命令，在存储器装置中建立设计块的实例的矩阵相对位置。这些实例之间的代表性连接响应于没有指定连接的用户输入的命令而在存储器装置中产生。

5. 发明授权

US08620638B1 Method of performing a simulation of a design under test and a circuit for enabling testing of a circuit design 有权
标题翻译：执行被测设计的仿真的方法和用于实现电路设计测试的电路
公开(公告)号：US08620638B1
公开(公告)日：2013-12-31
申请号：US12335025
申请日：2008-12-15
申请人： Chi Bun Chan , Jingzhao Ou , Shay Ping Seng , Nabeel Shirazi
发明人： Chi Bun Chan , Jingzhao Ou , Shay Ping Seng , Nabeel Shirazi
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5022
摘要： A method of performing a simulation of a design under test is disclosed. The method comprises implementing an input block having an adjustable output width; coupling test data to the input block; generating an input signal comprising the test data for the design under test according to an input requirement for the design under test by way of the input block; implementing an output block having an adjustable input width for receiving data from an output of the design under test; and coupling the output of the design under test to the output block according to an output requirement of the design under test. A circuit for enabling testing of a circuit design implemented in an integrated circuit is also disclosed.
摘要翻译：公开了一种对被测设计进行仿真的方法。该方法包括实现具有可调输出宽度的输入块; 将测试数据耦合到输入块; 根据输入块的被测设计的输入要求，生成包含被测设计的测试数据的输入信号; 实现具有可调输入宽度的输出块，用于从被测设计的输出接收数据; 并根据被测设计的输出要求将被测设计的输出耦合到输出块。还公开了一种能够测试在集成电路中实现的电路设计的电路。

6. 发明授权

US08600722B1 Method and apparatus for providing program-based hardware co-simulation of a circuit design 有权
标题翻译：用于提供电路设计的基于程序的硬件协同仿真的方法和装置
公开(公告)号：US08600722B1
公开(公告)日：2013-12-03
申请号：US11805133
申请日：2007-05-22
申请人： Chi Bun Chan , Nabeel Shirazi , Shay Ping Seng , Haibing Ma
发明人： Chi Bun Chan , Nabeel Shirazi , Shay Ping Seng , Haibing Ma
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： A method and apparatus for providing a program-based hardware co-simulation of a circuit design are described. In one example, a circuit design is implemented for programmable logic to establish a design under test (DUT). A co-simulation model is programmatically generated using primitives defined by an application programming interface (API). The circuit design is simulated by configuring the programmable logic with the DUT and driving a co-simulation engine to communicate with the DUT via execution of the co-simulation model.
摘要翻译：描述了一种用于提供电路设计的基于程序的硬件协同仿真的方法和装置。在一个示例中，实现用于可编程逻辑以建立被测设计（DUT）的电路设计。使用由应用程序编程接口（API）定义的原语以编程方式生成协同仿真模型。通过使用DUT配置可编程逻辑来模拟电路设计，并通过执行协同仿真模型驱动协同仿真引擎与DUT进行通信。

7. 发明授权

US07539953B1 Method and apparatus for interfacing instruction processors and logic in an electronic circuit modeling system 有权
标题翻译：用于在电子电路建模系统中连接指令处理器和逻辑的方法和装置
公开(公告)号：US07539953B1
公开(公告)日：2009-05-26
申请号：US11633977
申请日：2006-12-05
申请人： Shay Ping Seng , Jonathan B. Ballagh , Roger B. Milne , Bradley L. Taylor
发明人： Shay Ping Seng , Jonathan B. Ballagh , Roger B. Milne , Bradley L. Taylor
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Method, apparatus, and computer readable medium for circuit design is described. In one example, a model having at least one processor, at least one logic, and at least one shared memory is specified. The at least one shared memory is associated with the at least one processor. A memory map associated with the at least one shared memory and a bus adapter for coupling the memory map to the at least one processor are automatically generated.
摘要翻译：描述了用于电路设计的方法，装置和计算机可读介质。在一个示例中，指定具有至少一个处理器，至少一个逻辑和至少一个共享存储器的模型。所述至少一个共享存储器与所述至少一个处理器相关联。与至少一个共享存储器相关联的存储器映射和用于将存储器映射耦合到至少一个处理器的总线适配器被自动生成。

8. 发明授权

US07383478B1 Wireless dynamic boundary-scan topologies for field 有权
标题翻译：无线动态边界扫描拓扑领域
公开(公告)号：US07383478B1
公开(公告)日：2008-06-03
申请号：US11185118
申请日：2005-07-20
申请人： Jonathan B. Ballagh , Alexander Carreira , L. James Hwang , Roger B. Milne , Shay Ping Seng , Nabeel Shirazi
发明人： Jonathan B. Ballagh , Alexander Carreira , L. James Hwang , Roger B. Milne , Shay Ping Seng , Nabeel Shirazi
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/3025 , G01R31/318572 , H04W4/18 , H04W24/00 , H04W92/00
摘要： A programmable logic device (PLD) with a JTAG port, such as an FPGA, is provided with a wireless JTAG adapter to enable wireless communications. Multiple PLDs connected with wireless-to-JTAG adapters can be wirelessly linked in a network to form a large boundary-scan chain serial interface. To communicate with the PLDs having a wireless JTAG port, a host PC running application software is also equipped with a wireless transceiver.
摘要翻译：具有JTAG端口（例如FPGA）的可编程逻辑器件（PLD）提供有无线JTAG适配器以实现无线通信。与无线到JTAG适配器连接的多个PLD可以在网络中无线链接以形成大型边界扫描链串行接口。为了与具有无线JTAG端口的PLD通信，运行应用软件的主机PC还配备有无线收发器。

9. 发明授权

US08229725B1 Method and apparatus for modeling processor-based circuit models 有权
标题翻译：用于建模基于处理器的电路模型的方法和装置
公开(公告)号：US08229725B1
公开(公告)日：2012-07-24
申请号：US12240874
申请日：2008-09-29
申请人： Jingzhao Ou , Chi Bun Chan , Shay Ping Seng
发明人： Jingzhao Ou , Chi Bun Chan , Shay Ping Seng
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031 , G06F17/5059 , G06F2217/62 , G06F2217/84
摘要： Method and apparatus for modeling processor-based circuit models are described. Some examples relate to designing a circuit model having a processor system and custom logic. A bus adapter coupled to a bus of the processor system is generated. A shared memory interface between the custom logic and the bus adapter is generated. The shared memory interface includes a memory map for the processor system. A clock wrapper having a first clock input and a second clock input is generated. The first clock input drives the custom logic and first shared memory of the shared memory interface. The second clock input drives the processor system.
摘要翻译：描述了基于处理器的电路模型的方法和装置。一些示例涉及设计具有处理器系统和定制逻辑的电路模型。产生耦合到处理器系统的总线的总线适配器。生成自定义逻辑和总线适配器之间的共享存储器接口。共享存储器接口包括用于处理器系统的存储器映射。产生具有第一时钟输入和第二时钟输入的时钟包装器。第一个时钟输入驱动共享内存接口的自定义逻辑和第一个共享内存。第二个时钟输入驱动处理器系统。

10. 发明授权

US08024678B1 Interfacing with a dynamically configurable arithmetic unit 有权
标题翻译：与动态配置的运算单元接口
公开(公告)号：US08024678B1
公开(公告)日：2011-09-20
申请号：US12416333
申请日：2009-04-01
申请人： Bradley L. Taylor , Arvind Sundararajan , Shay Ping Seng , L. James Hwang
发明人： Bradley L. Taylor , Arvind Sundararajan , Shay Ping Seng , L. James Hwang
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： An interface to a dynamically configurable arithmetic unit can include data alignment modules, where each data alignment module receives input variables being associated with one or more arithmetic expressions. The interface can include multiplexers coupled to the data alignment modules, wherein a data alignment module has outputs coupled to a first multiplexer. The first multiplexer can have a selection line and an output coupled to an input port of the dynamically configurable arithmetic unit. The interface can include a second multiplexer having input instructions and the selection line, where each instruction is associated with one of the arithmetic expressions and has an operation to be performed by the dynamically configurable arithmetic unit. The second multiplexer is configurable to provide selected ones of the input instructions to the dynamically configurable arithmetic unit through an output of the second multiplexer responsive to the selection line.
摘要翻译：动态配置的算术单元的接口可以包括数据对准模块，其中每个数据对准模块接收与一个或多个算术表达式相关联的输入变量。接口可以包括耦合到数据对准模块的多路复用器，其中数据对准模块具有耦合到第一多路复用器的输出。第一复用器可以具有选择线和耦合到可动态配置的运算单元的输入端口的输出。接口可以包括具有输入指令和选择线的第二多路复用器，其中每个指令与算术表达式中的一个相关联，并且具有由可动态配置的运算单元执行的操作。第二多路复用器可配置成通过第二多路复用器的输出将响应于选择线的输入指令的选定输入指令提供给动态可配置的运算单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式