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1. 发明授权

US07003751B1 Specification of the hierarchy, connectivity, and graphical representation of a circuit design 有权
标题翻译：电路设计的层次结构，连接性和图形表示的规范
公开(公告)号：US07003751B1
公开(公告)日：2006-02-21
申请号：US10340498
申请日：2003-01-10
申请人： Jeffrey D. Stroomer , Roger B. Milne , Jonathan B. Ballagh , Haibing Ma , L. James Hwang , Nabeel Shirazi
发明人： Jeffrey D. Stroomer , Roger B. Milne , Jonathan B. Ballagh , Haibing Ma , L. James Hwang , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Method and apparatus for creating a circuit design. An object-oriented program instantiates a plurality of objects that model a circuit design. The objects have hierarchy attributes, connectivity attributes, and display attributes that describe a plurality of modules. The hierarchy attributes define parent-child relationships between modules, the connectivity attributes define input-output connections between modules, and the display attributes define a layout of the modules for viewing. Each of the objects has an associated method for generating a design specification in a selected format. When the program is executed, the design specification is generated from the set of objects. Depending on the capabilities of the available tools, the modules and logic elements are displayed in accordance with the display attributes either from the object-oriented program or from the design specification.
摘要翻译：用于创建电路设计的方法和装置。面向对象的程序实例化建模电路设计的多个对象。对象具有描述多个模块的层次属性，连接属性和显示属性。层次结构属性定义模块之间的父子关系，连接属性定义模块之间的输入输出连接，显示属性定义模块的布局以供查看。每个对象具有用于以所选格式生成设计规范的关联方法。当执行程序时，设计规范是从对象集合生成的。根据可用工具的功能，根据面向对象程序或设计规范的显示属性显示模块和逻辑元素。

2. 发明授权

US07203632B2 HDL co-simulation in a high-level modeling system 有权
标题翻译： HDL在高级建模系统中的共模拟
公开(公告)号：US07203632B2
公开(公告)日：2007-04-10
申请号：US10389161
申请日：2003-03-14
申请人： Roger B. Milne , L. James Hwang , Jeffrey D. Stroomer , Nabeel Shirazi , Haibing Ma , Jonathan B. Ballagh
发明人： Roger B. Milne , L. James Hwang , Jeffrey D. Stroomer , Nabeel Shirazi , Haibing Ma , Jonathan B. Ballagh
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.
摘要翻译：用于模拟包括高级组件和HDL组件的电路设计操作的方法和装置。设计的高级组件在高级建模系统（HLMS）中进行模拟，并且使用HDL模拟器来模拟设计的HDL组件。将数据值从HLMS的数据类型转换为与HDL模拟器兼容的逻辑向量，以将每个数据值输入到HDL模拟器，并且将逻辑向量从HDL模拟器转换为数据类型的数据值与HDL模拟器的每个逻辑矢量输出的HLMS兼容。根据HLMS事件的时间和HDL组件的最大响应时间，事件被安排输入到HDL模拟器。

3. 发明授权

US07478030B1 Clock stabilization detection for hardware simulation 有权
标题翻译：硬件仿真的时钟稳定检测
公开(公告)号：US07478030B1
公开(公告)日：2009-01-13
申请号：US10600848
申请日：2003-06-19
申请人： Jonathan B. Ballagh , Roger B. Milne , Jeffrey D. Stroomer , L. James Hwang , Nabeel Shirazi
发明人： Jonathan B. Ballagh , Roger B. Milne , Jeffrey D. Stroomer , L. James Hwang , Nabeel Shirazi
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5027 , G06F2217/62
摘要： Method and apparatus for clock stabilization detection for hardware simulation is described. More particularly, a lock signal is obtained, for example from a digital clock module. A least common multiple (LCM) clock signal is generated, for example from a clock module. A control signal is generated at least partially responsive to the LCM clock signal and the lock signal. The control signal may be generated from a state machine and applied to select circuitry, where the control signal is used to mask application of the output clock signal responsive to the control signal.
摘要翻译：描述了用于硬件模拟的时钟稳定检测的方法和装置。更具体地，例如从数字时钟模块获得锁定信号。例如从时钟模块产生最小公共多（LCM）时钟信号。至少部分地响应于LCM时钟信号和锁定信号产生控制信号。控制信号可以从状态机产生并应用于选择电路，其中控制信号用于响应于控制信号屏蔽输出时钟信号的应用。

4. 发明授权

US07437280B1 Hardware-based co-simulation on a PLD having an embedded processor 有权
标题翻译：具有嵌入式处理器的PLD上的基于硬件的协同仿真
公开(公告)号：US07437280B1
公开(公告)日：2008-10-14
申请号：US11016378
申请日：2004-12-16
申请人： Jonathan B. Ballagh , L. James Hwang , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer
发明人： Jonathan B. Ballagh , L. James Hwang , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： Co-simulation of an electronic circuit design using an embedded processor on a programmable logic device (PLD). The programmable logic resources of a PLD are used to perform hardware-based co-simulation of a first portion of the electronic circuit design. Software-based co-simulation of a second portion of the electronic circuit design is performed using the embedded processor.
摘要翻译：使用可编程逻辑器件（PLD）上的嵌入式处理器进行电子电路设计的协同仿真。 PLD的可编程逻辑资源用于执行电子电路设计的第一部分的基于硬件的协同仿真。使用嵌入式处理器执行电子电路设计的第二部分的基于软件的协同仿真。

5. 发明授权

US07363600B1 Method of simulating bidirectional signals in a modeling system 有权
标题翻译：在建模系统中模拟双向信号的方法
公开(公告)号：US07363600B1
公开(公告)日：2008-04-22
申请号：US10691343
申请日：2003-10-21
申请人： Jonathan B. Ballagh , Roger B. Milne , Jeffrey D. Stroomer , L. James Hwang , Nabeel Shirazi
发明人： Jonathan B. Ballagh , Roger B. Milne , Jeffrey D. Stroomer , L. James Hwang , Nabeel Shirazi
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022
摘要： A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.
摘要翻译：在支持单向数据流的高级建模系统中对设计建模的方法可以包括识别总线块以表示系统中双向总线的连接性。总线块可以与总线串联表示。分接头可以通过总线接口连接总线。在仿真期间，总线模块仿真与分接口的输入线串联的三态缓冲器的行为。在合成期间，可以模拟总线端口到总线块的相反数据路由取向的单向输入和输出线对可以被折叠到单个总线端口。该合成可以进一步生成可以在抽头输入和总线之间设置三态缓冲器的网表。网表还可以表示用于驱动水龙头输出的三态缓冲器的布局。

6. 发明授权

US07376544B1 Vector transfer during co-simulation 有权
标题翻译：矢量传输在协同仿真期间
公开(公告)号：US07376544B1
公开(公告)日：2008-05-20
申请号：US10777419
申请日：2004-02-12
申请人： Christopher H. Dick , Nabeel Shirazi , Roger B. Milne , Jeffrey D. Stroomer , Jonathan B. Ballagh
发明人： Christopher H. Dick , Nabeel Shirazi , Roger B. Milne , Jeffrey D. Stroomer , Jonathan B. Ballagh
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Various embodiments are disclosed for transferring data between blocks in a design during simulation. Operation of at least one high-level block in the design is simulated in a high-level modeling system (HLMS). A hardware-implemented block in the design is co-simulated on a hardware simulation platform. A first vector of data received by a co-simulation block is transferred to the simulated hardware-implemented block via a transfer function.
摘要翻译：公开了用于在模拟期间在设计中的块之间传送数据的各种实施例。在高级建模系统（HLMS）中模拟设计中至少一个高级块的操作。设计中的硬件实现块在硬件仿真平台上共同模拟。由模拟块接收的第一数据矢量通过传递函数被传送到模拟硬件实现的块。

7. 发明授权

US07346481B1 Hardware co-simulation breakpoints in a high-level modeling system 有权
标题翻译：硬件共模拟断点在高级建模系统中
公开(公告)号：US07346481B1
公开(公告)日：2008-03-18
申请号：US10930619
申请日：2004-08-31
申请人： Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer
发明人： Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5022 , G06F2217/62 , G06F2217/86
摘要： Various approaches for controlling simulation of an electronic system are disclosed. In one approach, at least one breakpoint block is instantiated in a high-level design. The breakpoint block has an associated breakpoint condition driven by at least one signal of the design, and the design further includes at least one simulation block and at least one co-simulation block. The simulation block is simulated on a software-based simulation platform, and the co-simulation block and the breakpoint block are co-simulated on a hardware-based co-simulation platform. Advancement of a clock signal to the co-simulation block on the hardware-based co-simulation platform is inhibited in response to satisfaction of the breakpoint condition. After inhibiting the clock signal, advancement of steps of the clock signal is controlled on the co-simulation platform in one of a plurality of user-selectable clock advancement modes.
摘要翻译：公开了用于控制电子系统的仿真的各种方法。在一种方法中，至少一个断点块在高级设计中被实例化。断点块具有由设计的至少一个信号驱动的相关联的断点条件，并且该设计还包括至少一个模拟块和至少一个协同模拟块。模拟块在基于软件的仿真平台上进行仿真，并且在基于硬件的协同仿真平台上共同模拟了共模拟块和断点块。响应于断点条件的满足，抑制了基于硬件的协同仿真平台上的协同仿真块的时钟信号的进展。在禁止时钟信号之后，以多个用户可选择的时钟提前模式之一在协同仿真平台上控制时钟信号的步长的前进。

8. 发明授权

US07546572B1 Shared memory interface in a programmable logic device using partial reconfiguration 有权
标题翻译：使用部分重新配置的可编程逻辑器件中的共享存储器接口
公开(公告)号：US07546572B1
公开(公告)日：2009-06-09
申请号：US11230879
申请日：2005-09-20
申请人： Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer
发明人： Jonathan B. Ballagh , Roger B. Milne , Nabeel Shirazi , Jeffrey D. Stroomer
IPC分类号： H03K17/693
CPC分类号： H03K19/17756 , H03K19/17732 , H03K19/1776
摘要： Partial reconfiguration of a programmable logic device is used in combination with a shared memory block for communicating between two blocks of an electronic circuit design. In one embodiment, a shared memory is implemented on RAM resources of a field programmable gate array (FPGA), and a first design block implemented in resources of the FPGA is coupled to the shared memory. A second design block is also coupled to the shared memory. In response to a write request by the second design block, a process determines the RAM resources of the FPGA that correspond to the shared memory address in the write request. A configuration bitstream is generated to include configuration data for partial reconfiguration of the FPGA with the data from the write request at the appropriate RAM resources. The FPGA is partially reconfigured with the configuration bitstream via a configuration port of the FPGA.
摘要翻译：可编程逻辑器件的部分重新配置与用于在电子电路设计的两个块之间进行通信的共享存储器块结合使用。在一个实施例中，在现场可编程门阵列（FPGA）的RAM资源上实现共享存储器，并且在FPGA的资源中实现的第一设计块耦合到共享存储器。第二设计块也耦合到共享存储器。响应于第二设计块的写请求，处理确定与写请求中的共享存储器地址相对应的FPGA的RAM资源。生成配置比特流以包括用于使用来自写入请求的数据在适当的RAM资源处对FPGA进行部分重新配置的配置数据。 FPGA通过FPGA的配置端口部分配置配置比特流。

9. 发明授权

US07086030B1 Incremental netlisting 有权
标题翻译：增量网页列表
公开(公告)号：US07086030B1
公开(公告)日：2006-08-01
申请号：US10633830
申请日：2003-08-04
申请人： Jeffrey D. Stroomer , Roger B. Milne , Haibing Ma , Jonathan B. Ballagh
发明人： Jeffrey D. Stroomer , Roger B. Milne , Haibing Ma , Jonathan B. Ballagh
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/86
摘要： Method and apparatus for preparing a design in a high-level modeling system. Hardware description language (HDL) code is generated for one or more of a plurality of high-level subsystems in a high-level design tagged by the user for HDL code generation. Previously generated HDL code may be reused instead of generating new HDL code for each subsystem tagged by the user for HDL code reuse.
摘要翻译：用于在高级建模系统中准备设计的方法和装置。为由HDL代码生成用户标记的高级设计中的多个高级子系统中的一个或多个生成硬件描述语言（HDL）代码。以前生成的HDL代码可以被重用，而不是为用户为HDL代码重用标记的每个子系统生成新的HDL代码。

10. 发明授权

US07934185B1 Method of simulating bidirectional signals in a modeling system 有权
标题翻译：在建模系统中模拟双向信号的方法
公开(公告)号：US07934185B1
公开(公告)日：2011-04-26
申请号：US12054247
申请日：2008-03-24
申请人： Jonathan B. Ballagh , Roger Brent Milne , Jeffrey D. Stroomer , L. James Hwang , Nabeel Shirazi
发明人： Jonathan B. Ballagh , Roger Brent Milne , Jeffrey D. Stroomer , L. James Hwang , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.
摘要翻译：在支持单向数据流的高级建模系统中对设计建模的方法可以包括识别总线块以表示系统中双向总线的连接性。总线块可以与总线串联表示。分接头可以通过总线接口连接总线。在仿真期间，总线模块仿真与分接口的输入线串联的三态缓冲器的行为。在合成期间，可以模拟总线端口到总线块的相反数据路由取向的单向输入和输出线对可以被折叠到单个总线端口。该合成可以进一步生成可以在抽头输入和总线之间设置三态缓冲器的网表。网表还可以表示用于驱动水龙头输出的三态缓冲器的布局。

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