专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08224638B1 Managing programmable device configuration 有权
标题翻译：管理可编程器件配置
公开(公告)号：US08224638B1
公开(公告)日：2012-07-17
申请号：US11650176
申请日：2007-01-05
申请人： Nabeel Shirazi , Chi Bun Chan , Bradley K. Fross , Shay Ping Seng , Jonathan B. Ballagh
发明人： Nabeel Shirazi , Chi Bun Chan , Bradley K. Fross , Shay Ping Seng , Jonathan B. Ballagh
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5054 , G06F2213/0038
摘要： A method of managing programmable device configuration can include running a server configuration image within the programmable device and storing a different configuration image within a non-volatile memory communicatively linked with the programmable device. Responsive to a switch request sent from the client to the programmable device over the communications link, the different configuration image can be loaded into the programmable device.
摘要翻译：管理可编程设备配置的方法可以包括在可编程设备内运行服务器配置图像并将不同的配置图像存储在与可编程设备通信地链接的非易失性存储器中。响应于通过通信链路从客户端发送到可编程设备的切换请求，可以将不同的配置图像加载到可编程设备中。

2. 发明授权

US07636653B1 Point-to-point ethernet hardware co-simulation interface 有权
标题翻译：点到点以太网硬件协同仿真界面
公开(公告)号：US07636653B1
公开(公告)日：2009-12-22
申请号：US11343367
申请日：2006-01-31
申请人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi , Roger B. Milne
发明人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi , Roger B. Milne
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5027
摘要： An Ethernet co-simulation interface for use with a software-based simulation tool and a design under test disposed on a programmable device can include a host interface and a network processor. The host interface can execute on a host computing system and facilitate data transfer between the software-based simulation tool and a communication link to the design under test. The network processor can be implemented within the programmable device and facilitate data transfer between the communication link and the design under test. The host interface and the network processor can exchange simulation data formatted as raw Ethernet frames over a point-to-point Ethernet connection.
摘要翻译：与可编程设备上的基于软件的仿真工具和被测设计一起使用的以太网协同仿真界面可以包括主机接口和网络处理器。主机接口可以在主机计算系统上执行，并促进基于软件的仿真工具与被测设计的通信链路之间的数据传输。网络处理器可以在可编程设备内部实现，并促进通信链路和被测设计之间的数据传输。主机接口和网络处理器可以通过点对点以太网连接交换格式化为原始以太网帧的模拟数据。

3. 发明授权

US07747423B1 Systems and methods of co-simulation utilizing multiple PLDs in a boundary scan chain 有权
标题翻译：在边界扫描链中利用多个PLD进行协同仿真的系统和方法
公开(公告)号：US07747423B1
公开(公告)日：2010-06-29
申请号：US11527841
申请日：2006-09-27
申请人： Nabeel Shirazi , Jonathan B. Ballagh , Chi Bun Chan
发明人： Nabeel Shirazi , Jonathan B. Ballagh , Chi Bun Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： Systems and methods of performing co-simulation of a partitioned circuit design using multiple programmable logic devices (PLDs) coupled together to form a boundary scan chain. A host computer is coupled to the scan chain via a programming cable. Resident on the host computer are run-time co-simulation blocks corresponding to blocks from the circuit design, where each block is designated to run on one of the PLDs in the scan chain; a programming cable device driver interfacing with the programming cable; and a proxy component. The proxy component is coupled to all of the run-time co-simulation blocks and the programming cable device driver. Each co-simulation block includes a unique pattern identifier, which is also present in the associated PLD. Using this pattern identifier, data and commands targeted to a specific PLD can be extracted from the scan chain, while ignoring data and commands targeted to other PLDs in the scan chain.
摘要翻译：使用耦合在一起以形成边界扫描链的多个可编程逻辑器件（PLD）执行分割电路设计的协同仿真的系统和方法。主机通过编程电缆耦合到扫描链。主计算机上的驻留是与电路设计中的块对应的运行时协同仿真块，其中每个块被指定为在扫描链中的一个PLD上运行; 与编程电缆接口的编程电缆设备驱动器; 和代理组件。代理组件耦合到所有运行时协同仿真模块和编程电缆设备驱动程序。每个共模拟块包括唯一的模式标识符，其也存在于相关联的PLD中。使用此模式标识符，可以从扫描链中提取针对特定PLD的数据和命令，同时忽略针对扫描链中其他PLD的数据和命令。

4. 发明授权

US07707019B1 Command buffering for hardware co-simulation 有权
标题翻译：用于硬件协同仿真的命令缓冲
公开(公告)号：US07707019B1
公开(公告)日：2010-04-27
申请号：US11234529
申请日：2005-09-23
申请人： Jonathan B. Ballagh , Chi Bun Chan , Nabeel Shirazi , Roger B. Milne
发明人： Jonathan B. Ballagh , Chi Bun Chan , Nabeel Shirazi , Roger B. Milne
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： A method of co-simulation involving a high level modeling system and an integrated circuit such as, e.g., a programmable logic device (PLD) can include, when writing to at least one input port of the PLD, storing a plurality of commands from a co-simulation engine within a command buffer and, responsive to a send condition, sending the plurality of commands to the PLD as a single transaction. When reading from at least one output port of the PLD, selectively reading from a cache external to the PLD or a memory of the PLD according to a state of cache coherency.
摘要翻译：涉及高级建模系统和诸如可编程逻辑器件（PLD）的集成电路的协同仿真的方法可以包括在写入PLD的至少一个输入端口时存储来自协同仿真引擎，并且响应于发送条件，将多个命令作为单个事务发送到PLD。当从PLD的至少一个输出端口读取时，根据高速缓存一致性的状态选择性地从PLD外部的高速缓存或PLD的存储器读取。

5. 发明授权

US08812289B1 Simulation that transfers port values of a design block via a configuration block of a programmable device 有权
标题翻译：模拟通过可编程设备的配置块传输设计块的端口值
公开(公告)号：US08812289B1
公开(公告)日：2014-08-19
申请号：US11732642
申请日：2007-04-04
申请人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
发明人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
IPC分类号： G06F9/455 , G06F17/50 , G06F11/36 , G06F17/22 , G06F11/267
CPC分类号： G06F17/5027 , G06F9/455 , G06F11/267 , G06F11/3652 , G06F17/22 , G06F17/5009 , G06F2217/86
摘要： Approaches for simulating an electronic system. In one approach, a software co-simulation platform is configured to produce a first time sequence of values of a plurality of input ports of a design block of the electronic system, consume a second time sequence of values of a plurality of output ports of the design block, and generate access transactions for transferring the first and second sequences of values. The software co-simulation platform generates a plurality of reconfiguration transactions for transferring reconfiguration data for the design block. A PLD is configured to implement a communication block and a control block. The communication block receives the reconfiguration and access transactions from the software co-simulation platform, and the control block reconfigures programmable logic and interconnect resources of the PLD in response to the reconfiguration transactions. The control block also controls the emulation of the design block in response to the access transactions.
摘要翻译：模拟电子系统的方法。在一种方法中，软件协同仿真平台被配置为产生电子系统的设计块的多个输入端口的值的第一时间序列，消耗电子系统的多个输出端口的值的第二时间序列并且生成用于传送第一和第二序列值的访问事务。软件协同仿真平台生成用于传送用于设计块的重新配置数据的多个重配置事务。 PLD被配置为实现通信块和控制块。通信块从软件协同仿真平台接收重新配置和访问事务，并且控制块响应于重新配置事务重新配置PLD的可编程逻辑和互连资源。响应于访问事务，控制块还控制设计块的仿真。

6. 发明授权

US07590137B1 Parameterizable compact network processor for low-level communication with an integrated circuit 有权
标题翻译：可配置的紧凑型网络处理器，用于与集成电路进行低级通信
公开(公告)号：US07590137B1
公开(公告)日：2009-09-15
申请号：US11285708
申请日：2005-11-22
申请人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
发明人： Chi Bun Chan , Jonathan B. Ballagh , Nabeel Shirazi
IPC分类号： H04J3/24
CPC分类号： G06F13/385 , G06F2213/3808
摘要： A network processor, disposed on an integrated circuit can include an ingress unit having a dual port block random access memory and an egress unit having a dual port block random access memory. The network processor further can include a network interface configured to write packetized data to the ingress unit and read packetized data from the egress unit as well as a coordination processor configured to coordinate movement of data between the network interface, the ingress unit, and the egress unit.
摘要翻译：设置在集成电路上的网络处理器可以包括具有双端口块随机存取存储器的入口单元和具有双端口块随机存取存储器的出口单元。网络处理器还可以包括被配置为将分组化数据写入入口单元并从出口单元读取分组化数据的网络接口以及配置为协调网络接口，入口单元和出口之间的数据移动的协调处理器单元。

7. 发明授权

US08868396B1 Verification and debugging using heterogeneous simulation models 有权
标题翻译：使用异构仿真模型进行验证和调试
公开(公告)号：US08868396B1
公开(公告)日：2014-10-21
申请号：US12605077
申请日：2009-10-23
申请人： Nabeel Shirazi , L. James Hwang , Chi Bun Chan , Hem C. Neema , Kumar Deepak
发明人： Nabeel Shirazi , L. James Hwang , Chi Bun Chan , Hem C. Neema , Kumar Deepak
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.
摘要翻译：本文公开了一种用于验证和调试高级编程系统的电路设计模块的方法和装置。在高级编程环境中创建的电路设计必须经过多次转换，因为它被编译成可以在硬件中实现的形式。在每个变换步骤中，必须用仿真模型验证电路的行为，并且如果转换改变了电路的行为，则进行调试。所要求保护的发明提出了一种用于在不同仿真模型之间验证和调试的新方法，并通过利用高级电路设计的模块化结构来实现本领域的进步，以系统地识别不同仿真模型之间的模拟不匹配并确定电路的哪些部分设计负责的差异。

8. 发明授权

US08102188B1 Method of and system for implementing a circuit in a device having programmable logic 有权
标题翻译：用于在具有可编程逻辑的设备中实现电路的方法和系统
公开(公告)号：US08102188B1
公开(公告)日：2012-01-24
申请号：US12757770
申请日：2010-04-09
申请人： Chi Bun Chan , Nabeel Shirazi
发明人： Chi Bun Chan , Nabeel Shirazi
IPC分类号： H03K19/173
CPC分类号： H03K19/17756 , H03K19/1776
摘要： A method of implementing a circuit in a device having programmable resources and a predetermined amount of available internal memory is disclosed. The method comprises configuring the programmable resources of the device with a circuit design; storing a first page of data in a block of random access memory; determining a page fault while interfacing with the block of random access memory when implementing the circuit design; performing a partial reconfiguration of the device, wherein a second page of data is stored in the block of random access memory; and accessing the second page of data. A system of implementing a circuit in a device having programmable logic is also disclosed.
摘要翻译：公开了一种在具有可编程资源和预定量的可用内部存储器的设备中实现电路的方法。该方法包括利用电路设计来配置设备的可编程资源; 将第一页数据存储在随机存取存储器块中; 当实现电路设计时，确定页面错误同时与随机存取存储器块接口; 执行所述设备的部分重新配置，其中第二数据页被存储在所述随机存取存储器块中; 并访问第二页数据。还公开了一种在具有可编程逻辑的设备中实现电路的系统。

9. 发明授权

US08402442B1 Common debugger method and system 有权
标题翻译：常用的调试器方法和系统
公开(公告)号：US08402442B1
公开(公告)日：2013-03-19
申请号：US12510810
申请日：2009-07-28
申请人： Chi Bun Chan , Jingzhao Ou , Nabeel Shirazi
发明人： Chi Bun Chan , Jingzhao Ou , Nabeel Shirazi
IPC分类号： G06F9/44 , G06F11/00
CPC分类号： G06F11/267 , G06F11/3664
摘要： Disclosed are approaches for operating a plurality of debugger tools. A common debugger receives first-type commands for processing. Each first-type command references one of the debugger tools. Each debugger tool provides control over a respective set of one or more components of the electronic system and recognizes a respective set of tool-specific commands. Each input first-type command is translated into a respective tool-specific command that is compatible with the one of the debugger tools specified in the first-type command. Each respective tool-specific command from the common debugger is provided to the one of the debugger tools specified in the input first-type command from which the respective tool-specific command was translated. Each translated tool-specific command is performed by the targeted debugger tool.
摘要翻译：公开了用于操作多个调试器工具的方法。一个常见的调试器接收第一个类型的命令进行处理。每个first-type命令引用一个调试器工具。每个调试器工具提供对电子系统的一个或多个组件的相应集合的控制，并识别相应的一组工具特定命令。每个输入第一类型命令被转换成与第一类型命令中指定的调试器工具兼容的相应的特定于工具的命令。来自公共调试器的每个相应的特定于工具的命令被提供给转换相应的特定于工具的命令的输入第一类型命令中指定的调试器工具之一。每个翻译的特定于工具的命令都由目标调试工具执行。

10. 发明授权

US08265918B1 Simulation and emulation of a circuit design 有权
标题翻译：电路设计的仿真和仿真
公开(公告)号：US08265918B1
公开(公告)日：2012-09-11
申请号：US12579846
申请日：2009-10-15
申请人： Hem C. Neema , Chi Bun Chan , Kumar Deepak , Nabeel Shirazi
发明人： Hem C. Neema , Chi Bun Chan , Kumar Deepak , Nabeel Shirazi
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5022
摘要： Co-simulation platforms generally include a software-based system and a hardware-based system in which different portions of the circuit design are either simulated in a software-based system or emulated on a hardware-based system. Before a model of circuit design can be co-simulated, the circuit design must be transformed and configured into a form that can execute and interface with a specific hardware-based system. The embodiments of the present invention provide a method, system, and article of manufacture for co-simulation of a portion of a circuit design and achieve an advance in the art by improving co-simulation configuration and setup and providing co-simulation adjustment capabilities during runtime.
摘要翻译：协同仿真平台通常包括基于软件的系统和基于硬件的系统，其中电路设计的不同部分在基于软件的系统中模拟或在基于硬件的系统上仿真。在电路设计模型可以共同模拟之前，电路设计必须被转换和配置成可以与特定的基于硬件的系统执行和接口的形式。本发明的实施例提供了一种用于对电路设计的一部分进行协同仿真的方法，系统和制品，并且通过改进协同仿真配置和设置并提供协同仿真调整能力来实现本领域的进步运行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式