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1. 发明授权

US4384327A Intersystem cycle control logic 失效
标题翻译：系统周期控制逻辑
公开(公告)号：US4384327A
公开(公告)日：1983-05-17
申请号：US223540
申请日：1981-01-08
申请人： John W. Conway , John J. Bradley , Kenneth E. Bruce , Ralph M. Lombardo, Jr. , Bruce H. Tarbox
发明人： John W. Conway , John J. Bradley , Kenneth E. Bruce , Ralph M. Lombardo, Jr. , Bruce H. Tarbox
IPC分类号： G06F13/36 , G06F13/40 , G06F9/46 , G06F3/04
CPC分类号： G06F13/4045 , G06F13/36 , G06F13/4027 , G06F13/404
摘要： A logic control system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein information may be transferred between plural communication busses while further information flow continues on each communication bus at the bus rate, and additional information transfers between the communication busses continue to be handled by the ISL unit.
摘要翻译：公开了一种在数据处理系统中在通信总线之间容纳二进制编码信息的传输的系统间链路（ISL）单元中的逻辑控制系统，其中可以在多个通信总线之间传送信息，同时在每个通信总线上继续进行信息流总线速率和通信总线之间的附加信息传输继续由ISL单元处理。

2. 发明授权

US4433376A Intersystem translation logic system 失效
标题翻译：系统翻译逻辑系统
公开(公告)号：US4433376A
公开(公告)日：1984-02-21
申请号：US216600
申请日：1980-12-15
申请人： Ralph M. Lombardo, Jr. , John J. Bradley , Kenneth E. Bruce , John W. Conway , David B. O'Keefe , Bruce H. Tarbox
发明人： Ralph M. Lombardo, Jr. , John J. Bradley , Kenneth E. Bruce , John W. Conway , David B. O'Keefe , Bruce H. Tarbox
IPC分类号： G06F13/36 , G06F13/40 , G06F3/04
CPC分类号： G06F13/36 , G06F13/4027 , G06F13/404
摘要： A logic system is provided for accommodating the exchange of information between two or more communication busses of a data processing system, wherein plural central processing units and plural memory units on independent communication busses may have same logic addresses. Memory and CPU addresses are translated at the bus rate through a multiplicity of flexible address translation ranges to enable a data processing unit on one communication bus to access an apparent contiguous range of addresses encompassing all data processing units on all communication busses.
摘要翻译：提供了一种用于容纳数据处理系统的两个或更多个通信总线之间的信息交换的逻辑系统，其中独立通信总线上的多个中央处理单元和多个存储器单元可以具有相同的逻辑地址。存储器和CPU地址通过多个灵活的地址转换范围以总线速率转换，以使得一个通信总线上的数据处理单元能够访问包含所有通信总线上的所有数据处理单元的明显的连续的地址范围。

3. 发明授权

US4236209A Intersystem transaction identification logic 失效
标题翻译：系统事务识别逻辑
公开(公告)号：US4236209A
公开(公告)日：1980-11-25
申请号：US956389
申请日：1978-10-31
申请人： Ralph M. Lombardo, Jr. , George J. Barlow , John J. Bradley , Kenneth E. Bruce , John W. Conway , Bruce H. Tarbox
发明人： Ralph M. Lombardo, Jr. , George J. Barlow , John J. Bradley , Kenneth E. Bruce , John W. Conway , Bruce H. Tarbox
IPC分类号： G06F13/36 , G06F13/40 , G06F13/42 , G06F3/04 , G06F13/00
CPC分类号： G06F13/36 , G06F13/4027 , G06F13/4213
摘要： A logic system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein dedicated locations in a file register are selected at the bus rate in response to binary coded information received from a local communication bus. ISL transactions to be initiated in response to bus cycle requests thereby are identified. ISL transactions are handled in parallel, and memory transfers are segregated from non-memory transfers to avoid unnecessary delays in memory transfers.
摘要翻译：公开了一种在数据处理系统中在通信总线之间容纳二进制编码信息的传输的系统间链路（ISL）单元中的逻辑系统，其中文件寄存器中的专用位置响应于从本地通讯总线。识别出响应于总线周期请求发起的ISL事务。 ISL事务被并行处理，并且内存传输与非内存传输隔离，以避免内存传输中不必要的延迟。

4. 发明授权

US4234919A Intersystem communication link 失效
标题翻译：系统间通信链路
公开(公告)号：US4234919A
公开(公告)日：1980-11-18
申请号：US956385
申请日：1978-10-31
申请人： Kenneth E. Bruce , George J. Barlow , John W. Conway , Ralph M. Lombardo, Jr. , John J. Bradley , David B. O'Keefe
发明人： Kenneth E. Bruce , George J. Barlow , John W. Conway , Ralph M. Lombardo, Jr. , John J. Bradley , David B. O'Keefe
IPC分类号： G06F13/36 , G06F13/40 , G06F13/42 , G06F3/04
CPC分类号： G06F13/36 , G06F13/4027 , G06F13/4213
摘要： A logic system referred to as an intersystem link unit (ISL) is provided for accommodating the transfer of binary coded information between two or more communication busses in a data processing system, wherein information including memory and non-memory read and write requests, CPU to CPU interrupts, peripheral control units to CPU interrupts may be transferred between plural communication busses each supporting plural data processing units including plural CPUs without substantially affecting the bus rate of the individual communication busses. Binary coded information from a communication bus is acquired asynchronously, and plural bus communications of different types are accommodated in parallel. The ISL units further may be dynamically reconfigured to provide for a reallocation of communication bus resources between communication busses.
摘要翻译：被称为系统间链路单元（ISL）的逻辑系统被提供用于在数据处理系统中的两个或多个通信总线之间容纳二进制编码信息的传送，其中包括存储器和非存储器读写请求的信息，CPU到 CPU中断，外围控制单元到CPU中断可以在多个通信总线之间传送，每个通信总线支持包括多个CPU的多个数据处理单元，而不会显着影响各个通信总线的总线速率。来自通信总线的二进制编码信息被异步地获取，并且并行地容纳不同类型的多个总线通信。还可以动态地重新配置ISL单元以提供通信总线之间的通信总线资源的重新分配。

5. 发明授权

US4717968A Video player with power-down capability 失效
标题翻译：具有断电功能的视频播放器
公开(公告)号：US4717968A
公开(公告)日：1988-01-05
申请号：US776239
申请日：1985-09-16
申请人： Richard C. Painton , Jay D. Marchetti , John J. Acello , John J. Bradley , Richard H. Bolton
发明人： Richard C. Painton , Jay D. Marchetti , John J. Acello , John J. Bradley , Richard H. Bolton
IPC分类号： G11B19/00 , G11B19/04 , G11B19/06 , G11B19/20 , H04N5/781
CPC分类号： G11B19/20 , G11B19/04 , G11B19/06
摘要： A video player includes a playback head that repeatedly passes in contact with a circular track on a flexible magnetic disk in order to reproduce a still picture on a video display. By cycling the player into a special quiescent state after a certain interval elapses without user instructions, excessive disk wear is avoided. While in the quiescent state, the disk drive motor is stopped--immobilizing the disk-to-head interface--and the video display is blanked. If user instructions are received while in this state, the disk drive motor is reenergized and the video display is resumed, showing the still picture displayed prior to interruption. If no user instructions are received during a further interval, the player is shut off.
摘要翻译：视频播放器包括在柔性磁盘上重复通过与圆形轨道接触的重放头，以便在视频显示器上再现静止图像。通过在没有用户指令的情况下经过一定间隔后，将播放器循环到特殊的静止状态，避免了过多的磁盘磨损。当处于静止状态时，磁盘驱动器电机停止 - 固定磁盘到磁头的接口 - 视频显示屏被消隐。如果在这种状态下接收到用户指令，则磁盘驱动电动机被重新通电并恢复视频显示，显示在中断之前显示的静止图像。如果在进一步的间隔期间没有接收到用户指令，则播放器被关闭。

6. 再颁专利

USRE32331E Method and apparatus for correcting stack lean in a zig-zag folded web 失效
标题翻译：用于校正锯齿形折叠纤维网中的摞倾斜的方法和装置
公开(公告)号：USRE32331E
公开(公告)日：1987-01-13
申请号：US656722
申请日：1984-10-01
申请人： James B. Fulk , Jerry L. McKeefry , George F. Schuning , John J. Bradley
发明人： James B. Fulk , Jerry L. McKeefry , George F. Schuning , John J. Bradley
IPC分类号： B26D5/22
CPC分类号： B26D5/22 , Y10T83/0424 , Y10T83/0481 , Y10T83/0519 , Y10T83/323 , Y10T83/6579
摘要： Method and apparatus for correcting stack lean in a zig-zag folded web wherein a transverse force is cyclically applied to a traveling web so as to vary the motion of the web slightly as it passes through a transverse perforator.

7. 发明授权

US4585507A Apparatus for making elastic diapers 失效
标题翻译：弹性尿布制造装置
公开(公告)号：US4585507A
公开(公告)日：1986-04-29
申请号：US718234
申请日：1985-04-01
申请人： John J. Bradley , John R. Merkatoris
发明人： John J. Bradley , John R. Merkatoris
IPC分类号： A61F13/15 , A61F13/16
CPC分类号： A61F13/15593 , Y10T156/101
摘要： Apparatus for producing elastic disposable diapers employing an oscillating fork means to V-fold longitudinally spaced portions of an adhesive equipped ribbon on itself to immobilize the adhesive in the spaced portions.
摘要翻译：用于制造使用摆动叉的弹性一次性尿布的装置用于将其自身上的粘合剂带状带的纵向间隔开的部分V形折叠，以将粘合剂固定在间隔开的部分中。

8. 发明授权

US4484271A Microprogrammed system having hardware interrupt apparatus 失效
标题翻译：具有硬件中断装置的微编程系统
公开(公告)号：US4484271A
公开(公告)日：1984-11-20
申请号：US392500
申请日：1982-06-28
申请人： Ming T. Miu , John J. Bradley , Jian-Kuo Shen
发明人： Ming T. Miu , John J. Bradley , Jian-Kuo Shen
IPC分类号： G06F9/26
CPC分类号： G06F9/268
摘要： A hardware interrupt apparatus for assigning the microprogrammed control system to the highest priority hardware interrupt requesting service. In a microprogrammed control system having at least one hardware interrupt, the presence of a hardware interrupt request will cause the interruption of the currently executing microprogram at the end of the current microinstruction. The address of the next microinstruction in the interrupted microprogram is saved in a hardware interrupt return address register and the next microinstruction address is generated as a function of the particular hardware interrupt to be serviced. A microprogram dedicated to servicing the particular hardware interrupt is then entered at the hardware interrupt generated next microinstruction address. Logic is provided within each microinstruction to inhibit hardware interrupts. Logic is provided within each microinstruction to indicate that the address of the next microinstruction should be taken from the hardware interrupt return address register, thereby allowing for the resumption of the interrupted microprogram. The hardware interrupt apparatus is further organized such that the entry to a second hardware interrupt service microprogram can be made upon the completion of a first hardware interrupt service microprogram without having to return to the original microprogram interrupted by the first hardware interrupt. Upon completion of the second hardware interrupt microprogram service routine, return can be made to the original microprogram interrupted by the first hardware interrupt.
摘要翻译：一种硬件中断装置，用于将微程序控制系统分配给最高优先级的硬件中断请求服务。在具有至少一个硬件中断的微程序控制系统中，存在硬件中断请求将导致在当前微指令结束时当前执行的微程序的中断。中断微程序中的下一个微指令的地址被保存在硬件中断返回地址寄存器中，并且根据要维护的特定硬件中断产生下一个微指令地址。然后在产生下一个微指令地址的硬件中断输入专用于维护特定硬件中断的微程序。在每个微指令内提供逻辑以禁止硬件中断。在每个微指令内提供逻辑，以指示下一个微指令的地址应从硬件中断返回地址寄存器中取出，从而允许恢复中断的微程序。硬件中断装置被进一步组织，使得可以在完成第一硬件中断服务微程序之后进入到第二硬件中断服务微程序，而不必返回到由第一硬件中断中断的原始微程序。在完成第二个硬件中断微程序服务程序后，可以返回由第一个硬件中断中断的原始微程序。

9. 发明授权

US4084224A System of controlling procedure execution using process control blocks 失效
标题翻译：使用过程控制块的控制程序执行系统
公开(公告)号：US4084224A
公开(公告)日：1978-04-11
申请号：US529018
申请日：1974-12-02
申请人： Marc Appell , John J. Bradley , Benjamin S. Franklin
发明人： Marc Appell , John J. Bradley , Benjamin S. Franklin
IPC分类号： G06F9/46 , G06F9/18
CPC分类号： G06F9/52
摘要： A system and method for computer process control in a multiprogramming/multiprocessing environment is disclosed. Each process in the system is associated with a process control block (PCB) hardware structure which is identified by its logical address (J,P). The PCB acts as a virtual processor with null speed when, in fact, no real processor is assigned to the process. As utilized in a multiprogramming environment a virtual process (PCB) is substituted for the real processor (i.e. central processing unit, CPU) whenever the only job of the processor is to listen for a signal to be sent by another processor and to restitute the real processor to the process when, or after, the signal has arrived. The circumstances where a process starts using a processor solely as an "ear" are as follows:A. when the process state switches from a running state to a waiting state; orB. when the process state switches from a running state to a suspended state.In both instances the CPU is given away and replaced by the PCB.

10. 发明授权

US4642109A Method of making elastic diapers and product 失效
标题翻译：制作弹性尿布和制品的方法
公开(公告)号：US4642109A
公开(公告)日：1987-02-10
申请号：US735056
申请日：1985-05-17
申请人： John J. Bradley , Debra K. Hansen
发明人： John J. Bradley , Debra K. Hansen
IPC分类号： A61F13/15 , A41B13/02
CPC分类号： A61F13/15593
摘要： A method for producing elastic disposable diapers, apparatus therefor and product therefrom which includes applying a continuous stripe of adhesive to stretched elastic ribbon, V-folding longitudinally spaced portions of the ribbon to immobilize the adhesive in the spaced portion, applying the intermediate flat portions of the stretched ribbon with exposed adhesive to a substrate, to form discreet diapers which have contractable portions therein.
摘要翻译：一种弹性一次性尿布的制造方法及其制造方法，其特征在于，包括对拉伸的弹性带施加连续条状的粘合剂，将所述带的V形折叠的纵向间隔的部分固定在所述间隔部分中，将所述粘合剂固定在所述间隔部分中，拉伸的带与裸露的粘合剂的基片，以形成其中具有可收缩部分的疏密的尿布。

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