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1. 发明授权

US4642109A Method of making elastic diapers and product 失效
标题翻译：制作弹性尿布和制品的方法
公开(公告)号：US4642109A
公开(公告)日：1987-02-10
申请号：US735056
申请日：1985-05-17
申请人： John J. Bradley , Debra K. Hansen
发明人： John J. Bradley , Debra K. Hansen
IPC分类号： A61F13/15 , A41B13/02
CPC分类号： A61F13/15593
摘要： A method for producing elastic disposable diapers, apparatus therefor and product therefrom which includes applying a continuous stripe of adhesive to stretched elastic ribbon, V-folding longitudinally spaced portions of the ribbon to immobilize the adhesive in the spaced portion, applying the intermediate flat portions of the stretched ribbon with exposed adhesive to a substrate, to form discreet diapers which have contractable portions therein.
摘要翻译：一种弹性一次性尿布的制造方法及其制造方法，其特征在于，包括对拉伸的弹性带施加连续条状的粘合剂，将所述带的V形折叠的纵向间隔的部分固定在所述间隔部分中，将所述粘合剂固定在所述间隔部分中，拉伸的带与裸露的粘合剂的基片，以形成其中具有可收缩部分的疏密的尿布。

2. 发明授权

US4543141A Method of making elastic diapers, apparatus therefor, and product 失效
标题翻译：弹性尿布的制造方法及其制造方法
公开(公告)号：US4543141A
公开(公告)日：1985-09-24
申请号：US565227
申请日：1983-12-27
申请人： John J. Bradley , Debra K. Hansen
发明人： John J. Bradley , Debra K. Hansen
IPC分类号： A61F13/494 , A61F5/44 , A61F13/15 , A61F13/49 , B31D1/04 , B65H45/22 , A61F13/16
CPC分类号： A61F13/15593 , Y10T156/101
摘要： A method for producing elastic disposable diapers, apparatus therefor and product therefrom which includes applying a continuous stripe of adhesive to stretched elastic ribbon, V-folding longitudinally spaced portions of the ribbon to immobilize the adhesive in the spaced portion, applying the intermediate flat portions of the stretched ribbon with exposed adhesive to a substrate, to form discrete diapers which have contractable portions therein.
摘要翻译：一种弹性一次性尿布的制造方法及其制造方法，其特征在于，包括对拉伸的弹性带施加连续条状的粘合剂，将所述带的V形折叠的纵向间隔的部分固定在所述间隔部分中，将所述粘合剂固定在所述间隔部分中，将具有暴露的粘合剂的拉伸带粘附到基底上，以形成其中具有可收缩部分的离散尿布。

3. 发明授权

US4717968A Video player with power-down capability 失效
标题翻译：具有断电功能的视频播放器
公开(公告)号：US4717968A
公开(公告)日：1988-01-05
申请号：US776239
申请日：1985-09-16
申请人： Richard C. Painton , Jay D. Marchetti , John J. Acello , John J. Bradley , Richard H. Bolton
发明人： Richard C. Painton , Jay D. Marchetti , John J. Acello , John J. Bradley , Richard H. Bolton
IPC分类号： G11B19/00 , G11B19/04 , G11B19/06 , G11B19/20 , H04N5/781
CPC分类号： G11B19/20 , G11B19/04 , G11B19/06
摘要： A video player includes a playback head that repeatedly passes in contact with a circular track on a flexible magnetic disk in order to reproduce a still picture on a video display. By cycling the player into a special quiescent state after a certain interval elapses without user instructions, excessive disk wear is avoided. While in the quiescent state, the disk drive motor is stopped--immobilizing the disk-to-head interface--and the video display is blanked. If user instructions are received while in this state, the disk drive motor is reenergized and the video display is resumed, showing the still picture displayed prior to interruption. If no user instructions are received during a further interval, the player is shut off.
摘要翻译：视频播放器包括在柔性磁盘上重复通过与圆形轨道接触的重放头，以便在视频显示器上再现静止图像。通过在没有用户指令的情况下经过一定间隔后，将播放器循环到特殊的静止状态，避免了过多的磁盘磨损。当处于静止状态时，磁盘驱动器电机停止 - 固定磁盘到磁头的接口 - 视频显示屏被消隐。如果在这种状态下接收到用户指令，则磁盘驱动电动机被重新通电并恢复视频显示，显示在中断之前显示的静止图像。如果在进一步的间隔期间没有接收到用户指令，则播放器被关闭。

4. 再颁专利

USRE32331E Method and apparatus for correcting stack lean in a zig-zag folded web 失效
标题翻译：用于校正锯齿形折叠纤维网中的摞倾斜的方法和装置
公开(公告)号：USRE32331E
公开(公告)日：1987-01-13
申请号：US656722
申请日：1984-10-01
申请人： James B. Fulk , Jerry L. McKeefry , George F. Schuning , John J. Bradley
发明人： James B. Fulk , Jerry L. McKeefry , George F. Schuning , John J. Bradley
IPC分类号： B26D5/22
CPC分类号： B26D5/22 , Y10T83/0424 , Y10T83/0481 , Y10T83/0519 , Y10T83/323 , Y10T83/6579
摘要： Method and apparatus for correcting stack lean in a zig-zag folded web wherein a transverse force is cyclically applied to a traveling web so as to vary the motion of the web slightly as it passes through a transverse perforator.

5. 发明授权

US4585507A Apparatus for making elastic diapers 失效
标题翻译：弹性尿布制造装置
公开(公告)号：US4585507A
公开(公告)日：1986-04-29
申请号：US718234
申请日：1985-04-01
申请人： John J. Bradley , John R. Merkatoris
发明人： John J. Bradley , John R. Merkatoris
IPC分类号： A61F13/15 , A61F13/16
CPC分类号： A61F13/15593 , Y10T156/101
摘要： Apparatus for producing elastic disposable diapers employing an oscillating fork means to V-fold longitudinally spaced portions of an adhesive equipped ribbon on itself to immobilize the adhesive in the spaced portions.
摘要翻译：用于制造使用摆动叉的弹性一次性尿布的装置用于将其自身上的粘合剂带状带的纵向间隔开的部分V形折叠，以将粘合剂固定在间隔开的部分中。

6. 发明授权

US4484271A Microprogrammed system having hardware interrupt apparatus 失效
标题翻译：具有硬件中断装置的微编程系统
公开(公告)号：US4484271A
公开(公告)日：1984-11-20
申请号：US392500
申请日：1982-06-28
申请人： Ming T. Miu , John J. Bradley , Jian-Kuo Shen
发明人： Ming T. Miu , John J. Bradley , Jian-Kuo Shen
IPC分类号： G06F9/26
CPC分类号： G06F9/268
摘要： A hardware interrupt apparatus for assigning the microprogrammed control system to the highest priority hardware interrupt requesting service. In a microprogrammed control system having at least one hardware interrupt, the presence of a hardware interrupt request will cause the interruption of the currently executing microprogram at the end of the current microinstruction. The address of the next microinstruction in the interrupted microprogram is saved in a hardware interrupt return address register and the next microinstruction address is generated as a function of the particular hardware interrupt to be serviced. A microprogram dedicated to servicing the particular hardware interrupt is then entered at the hardware interrupt generated next microinstruction address. Logic is provided within each microinstruction to inhibit hardware interrupts. Logic is provided within each microinstruction to indicate that the address of the next microinstruction should be taken from the hardware interrupt return address register, thereby allowing for the resumption of the interrupted microprogram. The hardware interrupt apparatus is further organized such that the entry to a second hardware interrupt service microprogram can be made upon the completion of a first hardware interrupt service microprogram without having to return to the original microprogram interrupted by the first hardware interrupt. Upon completion of the second hardware interrupt microprogram service routine, return can be made to the original microprogram interrupted by the first hardware interrupt.
摘要翻译：一种硬件中断装置，用于将微程序控制系统分配给最高优先级的硬件中断请求服务。在具有至少一个硬件中断的微程序控制系统中，存在硬件中断请求将导致在当前微指令结束时当前执行的微程序的中断。中断微程序中的下一个微指令的地址被保存在硬件中断返回地址寄存器中，并且根据要维护的特定硬件中断产生下一个微指令地址。然后在产生下一个微指令地址的硬件中断输入专用于维护特定硬件中断的微程序。在每个微指令内提供逻辑以禁止硬件中断。在每个微指令内提供逻辑，以指示下一个微指令的地址应从硬件中断返回地址寄存器中取出，从而允许恢复中断的微程序。硬件中断装置被进一步组织，使得可以在完成第一硬件中断服务微程序之后进入到第二硬件中断服务微程序，而不必返回到由第一硬件中断中断的原始微程序。在完成第二个硬件中断微程序服务程序后，可以返回由第一个硬件中断中断的原始微程序。

7. 发明授权

US4384327A Intersystem cycle control logic 失效
标题翻译：系统周期控制逻辑
公开(公告)号：US4384327A
公开(公告)日：1983-05-17
申请号：US223540
申请日：1981-01-08
申请人： John W. Conway , John J. Bradley , Kenneth E. Bruce , Ralph M. Lombardo, Jr. , Bruce H. Tarbox
发明人： John W. Conway , John J. Bradley , Kenneth E. Bruce , Ralph M. Lombardo, Jr. , Bruce H. Tarbox
IPC分类号： G06F13/36 , G06F13/40 , G06F9/46 , G06F3/04
CPC分类号： G06F13/4045 , G06F13/36 , G06F13/4027 , G06F13/404
摘要： A logic control system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein information may be transferred between plural communication busses while further information flow continues on each communication bus at the bus rate, and additional information transfers between the communication busses continue to be handled by the ISL unit.
摘要翻译：公开了一种在数据处理系统中在通信总线之间容纳二进制编码信息的传输的系统间链路（ISL）单元中的逻辑控制系统，其中可以在多个通信总线之间传送信息，同时在每个通信总线上继续进行信息流总线速率和通信总线之间的附加信息传输继续由ISL单元处理。

8. 发明授权

US4084224A System of controlling procedure execution using process control blocks 失效
标题翻译：使用过程控制块的控制程序执行系统
公开(公告)号：US4084224A
公开(公告)日：1978-04-11
申请号：US529018
申请日：1974-12-02
申请人： Marc Appell , John J. Bradley , Benjamin S. Franklin
发明人： Marc Appell , John J. Bradley , Benjamin S. Franklin
IPC分类号： G06F9/46 , G06F9/18
CPC分类号： G06F9/52
摘要： A system and method for computer process control in a multiprogramming/multiprocessing environment is disclosed. Each process in the system is associated with a process control block (PCB) hardware structure which is identified by its logical address (J,P). The PCB acts as a virtual processor with null speed when, in fact, no real processor is assigned to the process. As utilized in a multiprogramming environment a virtual process (PCB) is substituted for the real processor (i.e. central processing unit, CPU) whenever the only job of the processor is to listen for a signal to be sent by another processor and to restitute the real processor to the process when, or after, the signal has arrived. The circumstances where a process starts using a processor solely as an "ear" are as follows:A. when the process state switches from a running state to a waiting state; orB. when the process state switches from a running state to a suspended state.In both instances the CPU is given away and replaced by the PCB.

9. 发明授权

US4604722A Decimal arithmetic logic unit for doubling or complementing decimal operand 失效
标题翻译：十进制算术逻辑单元，用于加倍或补数十进制运算
公开(公告)号：US4604722A
公开(公告)日：1986-08-05
申请号：US537899
申请日：1983-09-30
申请人： Theodore R. Staplin, Jr. , John J. Bradley , Brian L. Stoffers
发明人： Theodore R. Staplin, Jr. , John J. Bradley , Brian L. Stoffers
IPC分类号： G06F7/48 , G06F7/491
CPC分类号： G06F7/491
摘要： A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is described. The CPU includes a microprocessor which executes the binary arithmetic software instructions under firmware control. Also disclosed is an arithmetic logic unit (ALU) that functions with the CPU. The ALU has operand inputs to which are connected switched steering circuits that permit particular operands and zero operands to be selectively applied to any or all of the ALU operand inputs. This allows easy performance of special arithmetic functions such as adding a decimal operand to itself when converting the decimal operand to a binary operand, and to subtract a decimal operand from zero when complementing decimal operands.
摘要翻译：描述了具有能够执行二进制和十进制算术软件指令的中央处理单元（CPU）的数据处理系统。 CPU包括在固件控制下执行二进制算术软件指令的微处理器。还公开了与CPU一起使用的算术逻辑单元（ALU）。 ALU具有操作数输入，连接的切换导向电路允许特定操作数和零操作数选择性地施加到ALU操作数输入中的任何一个或全部。这允许简单的执行特殊的算术运算功能，例如在将十进制操作数转换为二进制操作数时将其自身加一个十进制操作数，并在补零十进制操作数时从零中减去十进制操作数。

10. 发明授权

US4488227A Program counter stacking method and apparatus for nested subroutines and interrupts 失效
标题翻译：用于嵌套子程序和中断的程序计数器堆叠方法和装置
公开(公告)号：US4488227A
公开(公告)日：1984-12-11
申请号：US446748
申请日：1982-12-03
申请人： Ming T. Miu , John J. Bradley
发明人： Ming T. Miu , John J. Bradley
IPC分类号： G06F9/42 , G06F9/22 , G06F9/26 , G06F9/32 , G06F9/40
CPC分类号： G06F9/30054 , G06F9/268 , G06F9/4426
摘要： A computer system which facilitates the execution of nested subroutines and interrupts is disclosed. As each branch transfer within the program is executed by a control area logic, a microcommand initiates the transfer of the return address, which has been derived from the address in the present routine, to a first register of a push down stack. In addition, the microcommand also pushes down one level the contents of all of the registers in the stack containing previously stored return addresses. Thus, a sequential return to unfinished routines or subroutines is provided. When the subroutine or hardware interrupt service routine is completed, a code in the address field enables the return address of the previously branched from or interrupted routine to be retrieved from the first register in the push down stack and to provide it as the address of the next instruction to be executed. The retrieval of the return address from the push down stack also pops all other stored return addresses one level in the stack. In addition to providing multiple levels of subroutine and interrupt nesting, any number of subroutines or hardware interrupts may be partially completed since the last operating subroutine or hardware interrupt service routine is always the first one to be completed. Logic is also provided to detect the occurrence of a hardware interrupt during a return sequence such that the requirement to simultaneously push and pop the stack is properly handled.
摘要翻译：公开了一种便于执行嵌套子程序和中断的计算机系统。当程序内的每个分支传送由控制区域逻辑执行时，微指令启动已经从本例程中的地址导出的返回地址到下推堆栈的第一寄存器的传送。此外，微指令还将包含先前存储的返回地址的堆栈中的所有寄存器的内容推下一级。因此，提供了顺序返回到未完成的例程或子程序。当子程序或硬件中断服务程序完成时，地址字段中的代码使得先前分支的或中断的例程的返回地址能够从下推栈中的第一个寄存器检索，并将其提供为下一条要执行的指令。从下拉堆栈中检索返回地址也会在堆栈中弹出所有其他存储的返回地址一级。除了提供多级子程序和中断嵌套之外，任何数量的子程序或硬件中断可能会部分完成，因为最后一个操作子程序或硬件中断服务程序始终是第一个要完成的程序。还提供逻辑以在返回序列期间检测硬件中断的发生，从而适当地处理同时推送和弹出栈的要求。

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