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1. 发明授权

US4375036A Keyboard strobe generation system 失效
标题翻译：键盘频闪发生系统
公开(公告)号：US4375036A
公开(公告)日：1983-02-22
申请号：US157748
申请日：1980-06-09
申请人： Robert C. Miller , David B. O'Keefe
发明人： Robert C. Miller , David B. O'Keefe
IPC分类号： H03M11/02 , H03K17/56 , H03K5/00
CPC分类号： H03M11/02
摘要： A strobe generator in a data entry input device is responsive to an input strobe signal from a keyboard system to generate a strobe signal which is not affected by electrical noise produced by electrostatically or electromagnetically induced signals in the signal lines running between the keyboard system and the data entry device input logic. An accurate output strobe signal is generated by utilizing a retriggerable logic circuit to filter out noise signals of a duration shorter than a predetermined period. The predetermined period is chosen to be less than the minimum duration of a valid input strobe signal and greater than the duration of active noise signals. The strobe generator retains the output strobe signal in the active state by use of a flip-flop until the strobe generator receives a reset signal acknowledging that the output strobe signal has been sampled by the data entry device input logic. Once set, the flip-flop will remain set and its corresponding output strobe signal remain active until reset, even if subsequent input strobe signals of less than or greater than the predetermined period are received.
摘要翻译：数据输入输入设备中的选通发生器响应于来自键盘系统的输入选通信号，以产生不受在键盘系统和键盘系统之间运行的信号线中的静电或电磁感应信号产生的电噪声的选通信号的影响数据输入设备输入逻辑。通过利用可再触发逻辑电路来滤除短于预定周期的持续时间的噪声信号来产生精确的输出选通信号。选择预定周期小于有效输入选通信号的最小持续时间并且大于有效噪声信号的持续时间。选通发生器通过使用触发器将输出选通信号保持在激活状态，直到选通发生器接收到确认输出选通信号已被数据输入装置输入逻辑采样的复位信号为止。一旦设置，即使接收到小于或大于预定周期的后续输入选通信号，触发器将保持置位，并且其对应的输出选通信号保持有效直到复位。

2. 发明授权

US4298956A Digital read recovery with variable frequency compensation using read only memories 失效
标题翻译：使用只读存储器进行可变频率补偿的数字读取恢复
公开(公告)号：US4298956A
公开(公告)日：1981-11-03
申请号：US38977
申请日：1979-05-14
申请人： Donald J. Rathbun , David B. O'Keefe
发明人： Donald J. Rathbun , David B. O'Keefe
IPC分类号： H03M5/04 , G11B20/14 , H03M5/12 , H03M5/14 , H04L25/49 , G06F7/22 , G11B5/09
CPC分类号： G11B20/1423 , G11B20/1419
摘要： Digital data is recorded on the surface of a magnetic media such as a disk or diskette in the form of magnetic flux transitions identifying clock and data information in a modified frequency modulation (MFM) mode. A read head senses the flux transitions which are in turn converted to digital signals. A counter in the adapter starts to count when the adapter receives a digital signal. The count is transferred to a register and the counter presets when the adapter receives the next digital signal. The count is indicative of the time between the successive digital signals and should be representative of multiples of an integer. The count signals stored in the register address a read only memory whose output signals preset the counter to a value to compensate for the difference between the expected time and the actual time between the successive digital signals thereby reducing the read error rate.
摘要翻译：数字数据以磁通转换的形式记录在诸如磁盘或磁盘的磁介质的表面上，其以修改的频率调制（MFM）模式识别时钟和数据信息。读头检测通量转换，然后转换成数字信号。当适配器接收到数字信号时，适配器中的计数器开始计数。计数被传送到寄存器，并且当适配器接收到下一个数字信号时计数器预设。该计数表示连续的数字信号之间的时间，并且应该代表整数的倍数。存储在寄存器中的计数信号将一个只读存储器，其输出信号将计数器预置为一个值，以补偿预期时间和连续数字信号之间的实际时间之间的差异，从而降低读错误率。

3. 发明授权

US4003033A Architecture for a microprogrammed device controller 失效
标题翻译：微程序设备控制器的架构
公开(公告)号：US4003033A
公开(公告)日：1977-01-11
申请号：US643439
申请日：1975-12-22
申请人： David B. O'Keefe , Frank V. Cassarino, Jr. , Douglas L. Riikonen
发明人： David B. O'Keefe , Frank V. Cassarino, Jr. , Douglas L. Riikonen
IPC分类号： G06F9/22 , G06F9/26 , G06F3/00 , G06F15/16
CPC分类号： G06F9/226 , G06F9/26
摘要： A device controller having a microprogrammed control store for storing instructions useable in the control of the controller and a scratch pad memory for storing device specific information useable in the control and operation of the device is provided. An addressed instruction is received by an instruction register from which control signals are generated. The contents of the instruction register are used to address the control store as well as the scratch pad memory and in addition is received by means of a multiplexor by an arithmetic unit which provides computations in the controller. The multiplexor which in addition receives signals from the scratch pad memory and the devices is also directly coupled to write information in the scratch pad memory. The controller may receive diagnostic and other instructions from a coupled data processor which are then used to control the operation of the controller in place of the instructions in the control store.
摘要翻译：提供了一种具有微程序控制存储器的设备控制器，用于存储可用于控制器的指令和用于存储可用于设备的控制和操作的设备特定信息的便笺本式存储器。寻址指令由生成控制信号的指令寄存器接收。指令寄存器的内容用于对控制存储器以及暂存器存储器进行寻址，并且还通过在控制器中提供计算的算术单元通过多路复用器来接收。另外，从暂存器存储器和器件接收信号的多路复用器也直接耦合到在暂存器存储器中写入信息。控制器可以从耦合的数据处理器接收诊断和其它指令，然后这些指令用于控制控制器的操作来代替控制存储器中的指令。

4. 发明授权

US4520356A Display video generation system for modifying the display of character information as a function of video attributes 失效
标题翻译：显示视频生成系统，用于根据视频属性修改字符信息的显示
公开(公告)号：US4520356A
公开(公告)日：1985-05-28
申请号：US409774
申请日：1982-08-20
申请人： David B. O'Keefe , Robert C. Miller
发明人： David B. O'Keefe , Robert C. Miller
IPC分类号： G09G5/30 , G09G1/00
CPC分类号： G09G5/30
摘要： A video generation logic for a display controller includes a precoded PROM which combines visual attributes associated with the characters of information to be displayed on the display screen to produce multiple video control signals for modifying the dot pattern generation signal which is generated in response to character information stored in a refresh memory of the display controller. Visual attribute signals are used as an address to a video attribute generation PROM to retrieve a precoded data word associated with a particular combination of video attributes and the information contained in the retrieved data word is used to provide video control signals. Some of the video control signals are combined with the dot pattern generation signal to provide a video signal which is transmitted to the display monitor which displays the character information. One of the video attribute signals is a low intensity signal, which in the case of a character not having any other visual attributes selected, would result in the character of information being displayed in a reduced intensity level on the screen of the display monitor. Before transmission to the display monitor, this low intensity signal is modified by the video attribute generation PROM as a function of the other selected video attributes.
摘要翻译：用于显示控制器的视频产生逻辑器包括预编码的PROM，其将与要在显示屏幕上显示的信息的字符相关联的视觉属性组合以产生多个视频控制信号，用于修改响应于字符信息而产生的点图案生成信号存储在显示控制器的刷新存储器中。视觉属性信号被用作视频属性生成PROM的地址，以检索与特定视频属性组合相关联的预编码数据字，并且包含在检索的数据字中的信息用于提供视频控制信号。一些视频控制信号与点图案生成信号组合以提供视频信号，该视频信号被发送到显示字符信息的显示监视器。视频属性信号中的一个是低强度信号，在不具有任何其他视觉属性的字符的情况下，将导致在显示监视器的屏幕上以降低的强度水平显示信息的字符。在传输到显示监视器之前，该低强度信号被视频属性生成PROM修改为其他所选视频属性的函数。

5. 发明授权

US4338597A Remote monitor interface 失效
标题翻译：远程监控界面
公开(公告)号：US4338597A
公开(公告)日：1982-07-06
申请号：US127671
申请日：1980-03-06
申请人： Gordon L. Steiner , David B. O'Keefe , Robert C. Miller
发明人： Gordon L. Steiner , David B. O'Keefe , Robert C. Miller
IPC分类号： G09G1/16 , G09G5/30 , G09G1/00
CPC分类号： G09G1/165 , G09G5/30 , G09G2360/18
摘要： A data processing system remote monitor interface includes a first device which transmits different types of time-related information signals along multiple parallel channels to a second device for reception and combination into a different number of information signal outputs. The different types of digital information signals are synchronized by the first device prior to transmission to the second device. Components in the first device, the multiple parallel channels, and the second device are selected to maintain signal synchronization by minimizing signal skew thereby eliminating the necessity for signal resynchronization in the second device. The second device includes a receiver section which has a plurality of receivers. Each receiver operates to receive only one digital information signal and to pass the received signal onto its output. The received digital information signals are then amplified by an inverting amplifier prior to being combined into a different number of information signals which are then used by the receiving device. The system accommodates the transmission of synchronized digital information without requiring the transmission of any synchronizing information signal and without requiring the resynchronization of the information signals at the second device.
摘要翻译：数据处理系统远程监控接口包括第一设备，其沿着多个并行信道将不同类型的时间相关信息信号发送到第二设备，用于接收并组合成不同数量的信息信号输出。不同类型的数字信息信号在传输到第二设备之前由第一设备同步。选择第一设备中的组件，多个并行通道和第二设备以通过最小化信号偏移来维持信号同步，从而消除了在第二设备中的信号再同步的必要性。第二装置包括具有多个接收器的接收器部分。每个接收器操作以仅接收一个数字信息信号并将接收的信号传递到其输出。所接收的数字信息信号然后在被组合成不同数量的信息信号之前由反相放大器放大，然后由接收装置使用。该系统适应同步数字信息的传输，而不需要传输任何同步信息信号，而不需要在第二设备处重新同步信息信号。

6. 发明授权

US4000485A Data processing system providing locked operation of shared resources 失效
标题翻译：数据处理系统提供共享资源的锁定操作
公开(公告)号：US4000485A
公开(公告)日：1976-12-28
申请号：US591904
申请日：1975-06-30
申请人： George J. Barlow , Frank V. Cassarino, Jr. , John W. Conway , David B. O'Keefe
发明人： George J. Barlow , Frank V. Cassarino, Jr. , John W. Conway , David B. O'Keefe
IPC分类号： G06F9/46 , G06F9/52 , G06F13/00 , G06F13/36 , G06F13/368 , G06F13/378 , G06F13/42 , G06F9/18
CPC分类号： G06F13/4213 , G06F13/378
摘要： A central processing system which includes a plurality of units coupled over a common electrical bus for the transfer of information between any two units, includes one unit in which there is a shareable resource such as a memory for example. Apparatus is provided for any units to share such resource. Further apparatus is provided for enabling any of such units so sharing the resource to lock out any other unit which presents a specified control signal to the unit incorporating the resource.
摘要翻译：一种中央处理系统，其包括通过公共电气总线耦合以在任何两个单元之间传送信息的多个单元，包括一个单元，其中存在例如存储器等共享资源。为任何单位提供了共享这种资源的装置。提供了另外的装置，用于使任何这样的单元能够共享资源以将向控制信号提供特定控制信号的任何其它单元锁定到包含资源的单元。

7. 发明授权

US4433376A Intersystem translation logic system 失效
标题翻译：系统翻译逻辑系统
公开(公告)号：US4433376A
公开(公告)日：1984-02-21
申请号：US216600
申请日：1980-12-15
申请人： Ralph M. Lombardo, Jr. , John J. Bradley , Kenneth E. Bruce , John W. Conway , David B. O'Keefe , Bruce H. Tarbox
发明人： Ralph M. Lombardo, Jr. , John J. Bradley , Kenneth E. Bruce , John W. Conway , David B. O'Keefe , Bruce H. Tarbox
IPC分类号： G06F13/36 , G06F13/40 , G06F3/04
CPC分类号： G06F13/36 , G06F13/4027 , G06F13/404
摘要： A logic system is provided for accommodating the exchange of information between two or more communication busses of a data processing system, wherein plural central processing units and plural memory units on independent communication busses may have same logic addresses. Memory and CPU addresses are translated at the bus rate through a multiplicity of flexible address translation ranges to enable a data processing unit on one communication bus to access an apparent contiguous range of addresses encompassing all data processing units on all communication busses.
摘要翻译：提供了一种用于容纳数据处理系统的两个或更多个通信总线之间的信息交换的逻辑系统，其中独立通信总线上的多个中央处理单元和多个存储器单元可以具有相同的逻辑地址。存储器和CPU地址通过多个灵活的地址转换范围以总线速率转换，以使得一个通信总线上的数据处理单元能够访问包含所有通信总线上的所有数据处理单元的明显的连续的地址范围。

8. 发明授权

US4234919A Intersystem communication link 失效
标题翻译：系统间通信链路
公开(公告)号：US4234919A
公开(公告)日：1980-11-18
申请号：US956385
申请日：1978-10-31
申请人： Kenneth E. Bruce , George J. Barlow , John W. Conway , Ralph M. Lombardo, Jr. , John J. Bradley , David B. O'Keefe
发明人： Kenneth E. Bruce , George J. Barlow , John W. Conway , Ralph M. Lombardo, Jr. , John J. Bradley , David B. O'Keefe
IPC分类号： G06F13/36 , G06F13/40 , G06F13/42 , G06F3/04
CPC分类号： G06F13/36 , G06F13/4027 , G06F13/4213
摘要： A logic system referred to as an intersystem link unit (ISL) is provided for accommodating the transfer of binary coded information between two or more communication busses in a data processing system, wherein information including memory and non-memory read and write requests, CPU to CPU interrupts, peripheral control units to CPU interrupts may be transferred between plural communication busses each supporting plural data processing units including plural CPUs without substantially affecting the bus rate of the individual communication busses. Binary coded information from a communication bus is acquired asynchronously, and plural bus communications of different types are accommodated in parallel. The ISL units further may be dynamically reconfigured to provide for a reallocation of communication bus resources between communication busses.
摘要翻译：被称为系统间链路单元（ISL）的逻辑系统被提供用于在数据处理系统中的两个或多个通信总线之间容纳二进制编码信息的传送，其中包括存储器和非存储器读写请求的信息，CPU到 CPU中断，外围控制单元到CPU中断可以在多个通信总线之间传送，每个通信总线支持包括多个CPU的多个数据处理单元，而不会显着影响各个通信总线的总线速率。来自通信总线的二进制编码信息被异步地获取，并且并行地容纳不同类型的多个总线通信。还可以动态地重新配置ISL单元以提供通信总线之间的通信总线资源的重新分配。

9. 发明授权

US4320465A Digital frequency modulation and modified frequency modulation read recovery with data separation 失效
标题翻译：数字频率调制和修改频率调制读取恢复与数据分离
公开(公告)号：US4320465A
公开(公告)日：1982-03-16
申请号：US38767
申请日：1979-05-14
申请人： Donald J. Rathbun , David B. O'Keefe
发明人： Donald J. Rathbun , David B. O'Keefe
IPC分类号： H03M5/04 , G11B20/14 , H03M5/12 , H03M5/14 , H04L25/49 , G11B5/09 , G06F13/04
CPC分类号： G11B20/1423 , G11B20/1419
摘要： Digital data is recorded on the surface of a magnetic media such as a disk or diskette in the form of magnetic flux transitions identifying clock and data information in either a frequency modulation (FM) mode or a modified frequency modulation (MFM) mode. A read head senses the flux transitions which are in turn converted to digital signals. Apparatus converts the time between successive digital signals into PROM addresses. The PROM address locations store coded signals identifying the data as binary ONE or binary ZERO signals.
摘要翻译：数字数据以磁通量转换的形式记录在诸如磁盘或磁盘的磁介质的表面上，以频率调制（FM）模式或修改的频率调制（MFM）模式识别时钟和数据信息。读头检测通量转换，然后转换成数字信号。设备将连续数字信号之间的时间转换为PROM地址。 PROM地址位置将识别数据的编码信号存储为二进制1或二进制零信号。

10. 发明授权

US4236208A Test mode control logic system 失效
标题翻译：测试模式控制逻辑系统
公开(公告)号：US4236208A
公开(公告)日：1980-11-25
申请号：US956384
申请日：1978-10-31
申请人： David B. O'Keefe , Kenneth E. Bruce , Ralph M. Lombardo, Jr. , Bruce H. Tarbox , John W. Conway
发明人： David B. O'Keefe , Kenneth E. Bruce , Ralph M. Lombardo, Jr. , Bruce H. Tarbox , John W. Conway
IPC分类号： G06F11/27 , G06F13/40 , G06F13/42 , G06F3/04 , G06F11/22
CPC分类号： G06F13/4213 , G06F11/27 , G06F13/4027
摘要： A logic control system is disclosed for verifying the operability of memory and non-memory data and control paths in both local and remote intersystem link (ISL) units electrically interconnecting a local and remote communication bus in a data processing system. The data processing system may include two or more communication busses each pair of which are electrically interconnected by twin ISL units. The control logic architecture accommodates the receipt of a test mode command from a CPU on a local bus to initiate a test mode operation wherein the memory and non-memory data and control paths of both the local and the remote ISL units are excerised while on-line, and binary coded information received from the local bus is passed through the ISL units, onto the remote bus, and returned to a local bus memory resource for verification. No remote bus resources are used or affected, and the remote ISL unit shall ignore any communications received from any other data processing unit on the remote bus. The remote ISL unit is effectively non-existent to other data processing units on the remote bus.
摘要翻译：公开了用于验证在数据处理系统中电连接本地和远程通信总线的本地和远程系统间链路（ISL）单元中的存储器和非存储器数据和控制路径的可操作性的逻辑控制系统。数据处理系统可以包括两个或更多个通过双ISL单元电连接的通信总线。控制逻辑架构适应于从本地总线上的CPU接收测试模式命令以启动测试模式操作，其中本地和远程ISL单元的存储器和非存储器数据以及控制路径被切换，线路和从本地总线接收的二进制编码信息通过ISL单元传递到远程总线上，并返回到本地总线存储器资源进行验证。没有使用或影响远程总线资源，远程ISL单元将忽略从远程总线上任何其他数据处理单元接收到的任何通信。远程ISL单元实际上不存在于远程总线上的其他数据处理单元。

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